A 9 Transistor SRAM Featuring Array-level XOR Parallelism with Secure Data Toggling Operation

Yin, Zihan; Datta, Annewsha; Vijayakumar, Shwetha; Jacob, Ajey; Jaiswal, Akhilesh

doi:10.1145/3649476.3658789

Proceedings of the Great Lakes Symposium on VLSI 2024 2024

DOI: 10.1145/3649476.3658789

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A 9 Transistor SRAM Featuring Array-level XOR Parallelism with Secure Data Toggling Operation

Zihan Yin,

Annewsha Datta,

Shwetha Vijayakumar

et al.

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A 9 Transistor SRAM Featuring Array-level XOR Parallelism with Secure Data Toggling Operation

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References 18 publications

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