A background calibrated 28GS/s 8b interleaved SAR ADC in 28nm CMOS

Le, M.Q.; Gorecki, J.; Riani, J.; Pernillo, Jorge; Tan, A.; Gopalakrishnan, Karthik; Helal, Belal M.; Khandelwal, Pulkit; Loi, C.; Quek, Irene; Wong, Prudence W. H.; Buchwald, Aaron

doi:10.1109/cicc.2017.7993699

Cited by 10 publications

(1 citation statement)

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“…Although popular in telephony and instrumentation where data rate is typically low, SAR ADCs have re-established themselves as a promising ADC architecture inherently crafted for modern CMOS technologies. The emerging applications of SAR ADCs range from biomedical instruments where power consumption is of a great importance [4] to high-speed data links where conversion rate is pivotal [5,6], largely accredited to the full compatibility of SAR ADCs with technology scaling [7]. For example, in the low-power realm, SAR ADCs with kS/s rates and 10-bit resolution dissipate only a few micro watts [8,9,10,11].…”

Section: Introductionmentioning

confidence: 99%

A Digital-to-Time Converter for Time-Mode Successive-Approximation Register Analog-to-Digital Converters

Lee¹

2021

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file:///C:/Users/MWF/Downloads/Lee, Daniel Junehee.The 8-bit digital-to-time converter (DTC) to be used for a time-mode successive-approximation register analog-to-digital converter (SAR ADC) with a minimum power consumption and silicon area is presented. The architecture and the drawbacks of a conventional voltage-mode SAR ADC are discussed. The principle of time-mode circuits and benefits of their applications to mixed-signal circuits are explained. The architecture of a time-mode SAR ADC is presented. The need for an area and power-efficient DTC to be used for a time-mode SAR ADC is discussed. The principle of a DTC is explained and prior works on a DTC are reviewed. The principle of a phase interpolator (PI), to be used for a DTC, is explained and prior works on digital PIs are reviewed. The design of the proposed DTC is presented. Each block of the proposed DTC is explained using schematic and layout views. Optimal slope of the input of the PI and the condition for linear phase interpolation are investigated. Simulation results of the proposed DTC designed in TSMC 65 nm 1.0 V CMOS technology are provided. According to simulation results with BSIM4.4 device models only, the time resolution of 0.33 ps, a maximum operation frequency of 2.53 G Hz, the power consumption of 1.38 mW, and peak differential nonlinearity (DNL) and integral nonlinearity (INL) less than 0.14 least significant bit (LSB) and 0.49 LSB, respectively, for a nominal process (TT) and a temperature condition (27 C°) are achieved.

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