A BIST-based charge analysis for embedded memories

Abstract

We present a BIST architecture to perform Charge Based Analysis on embedded memories. The architecture includes a charge monitor as well as the input generation and output processing circuitry. The method applies a charge correlation technique validated experimentally on previous works for submicron SRAMs. The technique requires a short pre-characterization phase during manufacturing testing that guarantees process-variation immunity. The embedded BIST circuitry provides a digital output pass/fail flag that signals the result of the BISTcharge analysis.