A byte erasable 5V‐only 64 kbit EEPROM

Abstract

At present, the main products of highperformance EEPROMs which can beaccommodated in recent high-speed microcomputers are 16 K bit devices which require two supplies (Vee and Vpp). In this paper, a next generation EEPROM which can provide high performance and functionality such as: (1) high density (64 K bit); (2) byte erasable; and (3) internal programming supply is described. The memory device used is a reliable n-channel Si gate MNOS device .To realize a high density of 64 K, the miniaturization of the MNOS device has been examined, and the scaling law is proposed. Also, to accomplish a reli bl byte erasing, a timing is set up for a high-voltage switching circuit whose current supply capability is designed to have a sufficient margin so that the rate of high-voltage application into the memory array is determined approximately by the voltage multiplication rate of the multiplier circuit. The generation of high voltage is done by charge pumping method , and a z ner diode is used for th stabilization .