A Capacitor Mismatch Error Cancelation Technique for High-Speed High-Resolution Pipeline ADC

Abstract

An accurate gain-of-two amplifier, which successfully reduces the capacitor mismatch error is proposed. This amplifier has similar circuit complexity and linearity improvement to the capacitor error-averaging technique, but operates with two clock phases just like the conventional pipeline stage. This makes it suitable for high-speed, high-resolution analog-to-digital converters (ADCs). Two ADC architectures employing the proposed accurate gain-of-two amplifier are also presented. The simulation results show that the proposed ADCs can achieve 15-bit linearity with 8-bit capacitor matching.Keywords: Pipeline ADC, Calibration, Capacitor error-averaging, Spurious free dynamic range(SFDR), Signal to noise and distortion ratio(SNDR), Effective number of bit(ENOB).