A capacitor sharing technique for RSD cyclic ADC

A technique for reducing power dissipation in pipeline Analog-to-Digital converters (ADCs) is presented. The technique stems from the observation that the amplifier of the first stage is used to charge the input capacitors of the subsequent stage. At the end of the amplification phase, the feedback capacitor of the first stage holds the residue voltage across it and can be reused in the second stage. The feedback capacitor is designed to be a network of capacitor and switches. With appropriate clocking, the network is re-configured to form the input sampling network of the second stage. This reuse is combined with scaling down of the capacitors to result in more power savings.

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“…Simulation results were used to prove the soundness of the proposed technique. The technique has also been adapted to work in cyclic ADCs [7].…”

Section: Discussionmentioning

confidence: 99%

Simultaneous capacitor sharing and scaling for reduced power in pipeline ADCs

Malik

Geiger

2005

48th Midwest Symposium on Circuits and Systems, 2005.

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“…Owing to proper combination of gain switching, an overall gain range of 0 dB to 18 dB with 2 dB per step is obtained with appropriate decoding. A second-order 1.5 bit Σ-Δ modulator with capacitor sharing technique and three-level 1.5 bit quantizer is utilized in this design [32,33]. The modulator samples the input at a high rate for producing a binary output whose average value over time tracks the analog input, and it consists of a loop-filter that has a transfer function and a digital-to-analog converter (DAC) in the feedback path.…”

Section: Methodsmentioning

confidence: 99%

A Fully Integrated Sensor SoC with Digital Calibration Hardware and Wireless Transceiver at 2.4 GHz

Kim

Jang

Hwang

2013

Sensors

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A single-chip sensor system-on-a-chip (SoC) that implements radio for 2.4 GHz, complete digital baseband physical layer (PHY), 10-bit sigma-delta analog-to-digital converter and dedicated sensor calibration hardware for industrial sensing systems has been proposed and integrated in a 0.18-μm CMOS technology. The transceiver's building block includes a low-noise amplifier, mixer, channel filter, receiver signal-strength indicator, frequency synthesizer, voltage-controlled oscillator, and power amplifier. In addition, the digital building block consists of offset quadrature phase-shift keying (OQPSK) modulation, demodulation, carrier frequency offset compensation, auto-gain control, digital MAC function, sensor calibration hardware and embedded 8-bit microcontroller. The digital MAC function supports cyclic redundancy check (CRC), inter-symbol timing check, MAC frame control, and automatic retransmission. The embedded sensor signal processing block consists of calibration coefficient calculator, sensing data calibration mapper and sigma-delta analog-to-digital converter with digital decimation filter. The sensitivity of the overall receiver and the error vector magnitude (EVM) of the overall transmitter are −99 dBm and 18.14%, respectively. The proposed calibration scheme has a reduction of errors by about 45.4% compared with the improved progressive polynomial calibration (PPC) method and the maximum current consumption of the SoC is 16 mA.

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“…The op-amp is used only during the amplification phase where one op-amp can be employed by two stages. This op-amp sharing saves also power and area compared to other approaches like capacitor sharing (Soufi et al, 2005). Because of the low stage count the benefit of capacitor sharing is very small.…”

Section: Adc Architecturementioning

confidence: 97%

A 1.2 V 4.5 mW 10 bit 8 MS/s cyclic-ADC for mobile video and sensor applications

Trojer

Hebein

Krassnitzer

et al. 2009

Elektrotech. Inftech.

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A 10 bit 8 MS=s cyclic ADC without a dedicated sample and hold is presented. Op-amp sharing and a single ended reference buffer loaded with a resistive divider are used. For power saving the common-mode buffer was replaced by a simple low pass filter. The ADC consumes 4.5 mW and occupies 0.145 mm 2 . It is fabricated in a 130 nm 1.2 V CMOS process and achieves 57 dB SNDR for an 11 MHz input. The cyclic stage works with a 40 MHz clock which can be increased to 65 MHz where the effective number of bits is reduced to 8. A novel dynamic current switching technique is introduced to reduce the power consumption by 20%. The figure of merit (FOM) is about 0.37 pJ=conversion step.Ein 1,2 V 4,5 mW 10 bit 8 MS=s zyklischer ADC f € u ur mobiles Video und Sensoranwendungen. In diesem Beitrag wird ein 10 bit 8 MS=s zyklischer ADC ohne Abtast-und Halteglied pr€ a asentiert. Durch gemeinsame Ben€ u utzung eines Verst€ a arkers und eines unsymmetrischen Entkopplers, welcher mit einem resistiven Spannungsteiler belastet wird, wird Leistung gespart. Um weiter Leistung zu sparen, wurde der Gleichtaktverst€ a arkter durch ein einfaches Tiefpass-Filter ersetzt. Der ADC verbraucht 4,5 mW und beansprucht eine Fl€ a ache von 0,145 mm 2 . Dieser ADC wurde in einem 130 nm 1,2 V CMOS-Prozess gefertigt und erreicht ein Signal zu Rausch-und Verzerrungsabstand von 57 dB f€ u ur ein 11-MHz-Signal. Die zyklische Stufe arbeitet mit einem 40-MHz-Takt, welcher bis 65 MHz erh€ o oht werden kann, wobei die effektive Anzahl der Bits auf 8 reduziert wird. Ein neues dynamisches Stromschaltverfahren wird vorgestellt, welches den Stromverbrauch um 20 % reduziert und einen G€ u utefaktor von 0,37 pJ erm€ o oglicht. Schl€ u usselw€ o orter: portables Video; mobiles Video; zyklischer ADC; niedrige Leistung; gemeinsame Ben€ u utzung eines Verst€ a arkers

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A capacitor sharing technique for RSD cyclic ADC

Cited by 10 publications

References 4 publications

Simultaneous capacitor sharing and scaling for reduced power in pipeline ADCs

Simultaneous capacitor sharing and scaling for reduced power in pipeline ADCs

A Fully Integrated Sensor SoC with Digital Calibration Hardware and Wireless Transceiver at 2.4 GHz

A 1.2 V 4.5 mW 10 bit 8 MS/s cyclic-ADC for mobile video and sensor applications

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