A Case Study of Using IEEE P1687 (IJTAG) for High-Speed Serial I/O Characterization and Testing

Rearick, Jeff; Volz, A.

doi:10.1109/test.2006.297620

Cited by 33 publications

(24 citation statements)

References 5 publications

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“…To setup the scan-path, P1687 proposes to transport SIB control data together with instrument data on a single wire (the JTAG scan-path), and this will affect overall access time (OAT). The work on IEEE P1687 is on-going and not yet ratified, and only a few studies have considered it [4], [7], [8], [9], [10]. We will discuss and compare JTAG and IJTAG from a hardware perspective, and elaborate on challenges related to the introduced flexibility and scalability.…”

Section: Ieee 31st Vlsi Test Symposium (Vts)mentioning

confidence: 99%

“…However, there is a lack of flexibility and scalability. The IEEE P1687 standard proposal [2], [3], [4], [5], [6] aims to address the need of standardization, by describing a flexible data transport infrastructure (called network) to interface JTAG to the chip internal instruments. P1687 has therefore received the informal name of Internal JTAG (IJTAG).…”

Section: Introductionmentioning

confidence: 99%

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Special session 9B: Embedded tutorial embedded DfT instrumentation: Design, access, retargeting and case studies

Larsson

2013

2013 IEEE 31st VLSI Test Symposium (VTS)

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Abstract:As semiconductor technologies enables highly advanced an complex integrated circuits (ICs), there is an increasing need to have more embedded design-for-test (DfT) instruments for test, debug, diagnosis, configuration, monitoring, etc. As these instruments are to be used not only at chip-level but also at board-level and system-level, a key challenge is how to access these instruments from chip terminals in a low-cost, non-intrusive, standardized, flexible and scalable manner. The well-adopted IEEE 1149.1 (Joint Test Action Group (JTAG)) standard offers lowcost, non-intrusive and standardized access but lacks flexibility and scalability, which is addressed by the on-going IEEE P1687 (Internal JTAG (IJTAG)) standardization initiative. We will discuss the need of embedded instrumentation, the shortcomings of IEEE 1149.1, the features and challenges of IEEE P1687, as well as cases studies on the usage of IEEE P1687.

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Section: Ieee 31st Vlsi Test Symposium (Vts)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Special session 9B: Embedded tutorial embedded DfT instrumentation: Design, access, retargeting and case studies

Larsson

2013

2013 IEEE 31st VLSI Test Symposium (VTS)

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“…Since IEEE P1687 has recently been proposed, only a few studies have considered it [3], [4], [5], [6]. However, no study has considered automated design of optimized P1687 networks.…”

Section: Overview Of P1687 and Review Of Prior Workmentioning

confidence: 99%

“…In [3] and [4], the authors proposed techniques for testing IEEE 1500 wrapped cores and have considered future integration of those techniques with P1687. In [5], a case study for test and configuration of high-speed serial I/O (HSSIO) links using P1687 is presented. There, it is mentioned that due to the need for high-volume manufacturing test of HSSIO links and difficulties associated with external test equipments, using onchip test instruments will be an attractive solution.…”

Section: Overview Of P1687 and Review Of Prior Workmentioning

confidence: 99%

“…There, it is mentioned that due to the need for high-volume manufacturing test of HSSIO links and difficulties associated with external test equipments, using onchip test instruments will be an attractive solution. However, in [5] accessing P1687 instruments through JTAG TAP is regarded as a bottleneck, from which it can be inferred that instrument access time is an important parameter for optimization. According to [5] accessing the on-chip instruments can be done individually or in unison.…”

Section: Overview Of P1687 and Review Of Prior Workmentioning

confidence: 99%

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Design automation for IEEE P1687

Zadegan

Ingelsson

Carlsson

et al. 2011

2011 Design, Automation &Amp; Test in Europe

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Abstract-The IEEE P1687 (IJTAG) standard proposal aims at standardizing the access to embedded test and debug logic (instruments) via the JTAG TAP. P1687 specifies a component called Segment Insertion Bit (SIB) which makes it possible to construct a multitude of alternative P1687 instrument access networks for a given set of instruments. Finding the best access network with respect to instrument access time and the number of SIBs is a time-consuming task in the absence of EDA support. This paper is the first to describe a P1687 design automation tool which constructs and optimizes P1687 networks. Our EDA tool, called PACT, considers the concurrent and sequential access schedule types, and is demonstrated in experiments on industrial SOCs, reporting total access time and average access time.

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