A cell-based design approach for RSFQ circuits using a binary decision diagram

Yoshikawa, Nobuyuki; Koshiyama, Junichi

doi:10.1088/0953-2048/12/11/327

Cited by 9 publications

(4 citation statements)

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“…All these features are suitable for employing a cell-based design methodology. We have proposed a cell-based design approach based on the BDD [3] and made a BDD RSFQ standard cell library [4]. The main features of our cell-based design approach are as follows: (i) The standard cell library is composed of limited number of basic cells, such as Line, Cross, Fork, Join and Bina.…”

Section: A Cell-based Design Methodology For Bdd Rsfq Logic Circuitsmentioning

confidence: 99%

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Cell-based design methodology for BDD RSFQ logic circuits: tolerance of basic cells to circuit parameter variations

Yoshikawa¹,

Yoda²,

Hoshina³

et al. 2001

Supercond. Sci. Technol.

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We have proposed a cell-based design approach based on a binary decision diagram (BDD) for the design of rapid single flux quantum (RSFQ) logic circuits. In this design approach, any logic function can be implemented by simply embedding the limited number of basic cells. We have constructed a BDD RSFQ cell library and prepared a top-down CAD environment. In this study, we investigated the tolerance of the BDD RSFQ basic cells to the circuit parameter variations. It was found that theoretical and measured dc bias margins of the basic cells agree well if we assume appropriate parameter variations due to the fabrication process. The dependence of the dc bias margin of the circuits on the circuit size was also examined, where we have implemented a 2-bit multiplexer, a 4-bit data-driven self-timed shift register and a 1-bit ALU. The low-speed test results reveal that dc bias margin of the circuits containing several hundreds of Josephson junctions is about ±15%, whereas theoretical dc bias margin is about ±33%.This paper was presented at the 8th International Superconductive Electronics Conference, Osaka, Japan, 19–22 June 2001.

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Section: A Cell-based Design Methodology For Bdd Rsfq Logic Circuitsmentioning

confidence: 99%

“…We have proposed a cell-based design approach based on a binary decision diagram (BDD) [2] and implemented a BDD RSFQ standard cell library [3,4]. In our design approach, any logic function can be implemented by simply embedding the limited number of basic cells.…”

Section: Introductionmentioning

confidence: 99%

Cell-based design methodology for BDD RSFQ logic circuits: tolerance of basic cells to circuit parameter variations

Yoshikawa¹,

Yoda²,

Hoshina³

et al. 2001

Supercond. Sci. Technol.

Self Cite

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“…We have developed a cell-based design approach for the BDD SFQ logic gate [3], and made a BDD SFQ cell library for the Hypres standard Nb process [8]. The BDD cells have also been added to the CONNECT cell library [9] for the NEC Nb standard process.…”

Section: Bdd Sfq Logic Circuits and Cell Librarymentioning

confidence: 99%

“…We have proposed a cell-based design approach [3] based on a binary decision diagram (BDD) [4] and made a BDD SFQ standard cell library [5]. A top-down CAD environment [6] is also developed to assist the large-scale circuit design.…”

Section: Introductionmentioning

confidence: 99%

Cell based design methodology for BDD SFQ logic circuits: A high speed test and feasibility for large scale circuit applications

Yoshikawa

Yoda

Hoshina

et al. 2003

IEEE Trans. Appl. Supercond.

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We have proposed a cell-based design methodology for SFQ logic circuits based on a binary decision diagram (BDD) and implemented a BDD SFQ standard cell library using a Hypres Nb process. In this design methodology, any logic function can be implemented by connecting binary switches. Since the circuits are dual rail logic and don't need a global clock, difficulty in the timing design is reduced considerably. In our cell-based design approach, the cell library is composed of only five kinds of basic cells, whose circuit parameters are optimized so as to remove the inter-cell interaction. In the layout level, the cells have the identical size so that circuits can be implemented by simply embedding the basic cells. In this study we have performed an on-chip high-speed test of the BDD SFQ logic circuits. The test system consists of two four-bit data-driven self-timed (DDST) shift registers with a ladder type clock generator. We have confirmed 12 GHz operations of the BDD SFQ logic circuit. We have also examined circuit size dependence of the DC bias margin of large BDD SFQ circuits.Index Terms-Binary decision diagram, cell base design, cell library, RSFQ, superconducting circuits.

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