A cellular architecture for memristive stateful logic

Abstract

In this paper, we present a CMOS/memristor hybrid architecture for massively parallel logic computations in a CMOL-type memristive memory. The considered architecture enables bit-parallel stateful logic operations, which can be used to efficiently implement vector computations. As examples of computing schemes that benefit from the considered processing architecture, we consider the implementation of a content-addressable memory and binary cellular automata. We verify the correct operation of the considered processing architecture and algorithms using HSPICE simulations.

A spintronic memristor bridge synapse circuit and the application in memrisitive cellular automata

“…According to the Refs. [24][25][26][27][28][29][30][31][32][33][34][35][36][37], in the study of cellular automata networks, the cell structure design is quite perfect. They can perform logical operations, image processing operations, complex behavior, etc.…”