A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration

Lee, Kyeongho; Cheon, Sungsoo; Jo, Joongho; Choi, Woong; Park, Jongsun

doi:10.1109/dac18074.2021.9586103

Cited by 13 publications

(5 citation statements)

References 15 publications

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“…In this expression, A 1 coefficient, which is the always-active energy consumption, and A 2 coefficient, which is the static energy consumption, are combined with AF(%) to estimate the energy consumption. To illustrate the whole model, the extended version of (9) can be seen in (10).…”

Section: Energy Modelingmentioning

confidence: 99%

“…As a reminder, for q = [a, b] mapping, the multi-bit values in the dataset are quantized into the integers between a and b. Afterwards, the energy estimation model matrix E(Q) is created for each quantization map by substituting each Q i,j into (10). Finally, energy estimated by the model (E(Q)) and energy simulated by NeuroSim (Sim(Q)) are compared.…”

Section: Comparison Of Proposed Analytical Model Against Neurosimmentioning

confidence: 99%

“…Here, each storage element implements single-bit multiplication, which is a part of a larger operation [5]. By employing different types of arithmetic units in memory cells, various types of IMC architectures were developed in [5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23]. These works aim to improve energy consumption, speed, and accuracy.…”

Section: Introductionmentioning

confidence: 99%

“…These works aim to improve energy consumption, speed, and accuracy. Additionally, inputs with different resolutions, ranging from single-bit precision in [5,6,19] to multi-bit precision, were used [7][8][9][10][11][12] to satisfy the accuracy criteria of various types of neural networks [7]. In addition to these, there are studies carried out at the device level to realize lower-power IMC architectures based on different types of memory cells [24,25].…”

Section: Introductionmentioning

confidence: 99%

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An Energy Consumption Model for SRAM-Based In-Memory-Computing Architectures

Akgül,

Karalar

2024

Electronics

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In this paper, a mathematical model for obtaining energy consumption of IMC architectures is constructed. This model provides energy estimation based on the distribution of a specific dataset. In addition, the estimation reduces the required simulation time to create an energy consumption model of SRAM-based IMC architectures. To validate our model with realistic data, the energy consumption of IMC is compared by using NeuroSim V3.0 for the CIFAR-10 and MNIST-like datasets. Furthermore, an application is created with our model to select highest performing quantization mapping based upon the parameters of energy consumption and accuracy.

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Section: Energy Modelingmentioning

confidence: 99%

Section: Comparison Of Proposed Analytical Model Against Neurosimmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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An Energy Consumption Model for SRAM-Based In-Memory-Computing Architectures

Akgül,

Karalar

2024

Electronics

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“…There are mainly two types of CIM readout circuits for analog types: the traditional ADC type and the non-traditional type. For the first type, [3] features a variable precision circuit based on split-capacitance for 5/6 bit accuracy. This design reduces the ADC area by employing split-capacitance in the DAC and adjusting the total capacitance at the DAC output node by controlling the MSB capacitor.…”

Section: Introductionmentioning

confidence: 99%

Readout Circuit Design for RRAM Array-Based Computing in Memory Architecture

Xu,

Wang,

Shui

2024

Electronics

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In recent advancements, the traditional von Neumann architecture has been challenged by the computational needs of AI. This is due to its high power and data transfer costs. As a solution, the computing-in-memory (CIM) architecture, which combines storage and computation, has gained attention for its superior computational power and energy efficiency. Within CIM, using resistive random access memory (RRAM) arrays, the readout circuit, which converts analog outputs from multiply–accumulate operations into digital signals, faces limitations due to its area and power consumption. There are mainly two types of CIM readout circuits for analog types: the traditional ADC type and the non-traditional type. This paper presents two types of readout circuit designs. The first is a low-power, compact successive approximation register (SAR) analog-to-digital converter (ADC) readout circuit. The core circuit is an 8-bit SAR ADC operating at 70 MS/s. It incorporates a linearity-improved bootstrapped switch to minimize leakage and enhance linearity, whose spurious-free dynamic range (SFDR) has been improved by 10.1 dB from 76.78 dB to 86.88 dB, and whose signal-to-noise and distortion ratio (SNDR) has increased by 4.56 dB from 75.13 dB to 79.69 dB. The delay of a transconductance-enhanced dynamic comparator is reduced from 184 ps to 149 ps, presenting a performance improvement of approximately 20%. Concurrently, the energy consumption decreased from 178 μm to 132 μm, attaining an improvement of roughly 26%. A “sandwich” capacitor structure is used that reduces the overall area of the layout. After layout and post-simulation, this circuit occupies only 49.6 μm × 51.5 μm, consumes 553 μW power, has a SINAD of 46.22 dB, and has an SFDR of 57.21 dB. The second is a current controlled oscillator (CCO)-type readout circuit, which comprises a CCO oscillator with low process-sensitivity. The readout circuit also utilizes an op-amp and current mirrors for a negative feedback loop, ensuring a constant voltage across the RRAM arrays. The frequency generated through the CCO is controlled by the current, and quantified by a counter, supporting different weights quantification per ReRAM column without additional digital weighting. This circuit achieves 95-level resolution, 5.2 μs delay, and an average consumption of 183.1 μW. A comparative analysis highlights that traditional ADC readout circuits offer high resolution and speed but are limited by their high power and area costs, often overshadowing CIM arrays’ benefits. Thus, for applications with more lenient resolution and speed requirements, non-traditional readout circuits present considerable advantages.

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