A chip-level post-CMOS via-last Cu TSV process for multi-layer homogeneous 3D integration

Eroglu, Seniz Esra Kucuk; Cho, Woo Yeong; Leblebici, Yusuf

doi:10.1109/prime.2016.7519491

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A chip-level post-CMOS via-last Cu TSV process for multi-layer homogeneous 3D integration

Cited by 3 publications

References 13 publications

Copper TSV-based die-level via-last 3D integration process with parylene-C adhesive bonding technique

Copper TSV-based die-level via-last 3D integration process with parylene-C adhesive bonding technique

Scaling a Fluorescent Detection System by Polymer-Assisted 3-D Integration of Heterogeneous Dies

Effect of Substrate Transfer on Performance of Vertically Stacked Ultrathin MOS Devices

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