A circuit representation technique for automated circuit design

Lohn, Jason; Colombano, Silvano

doi:10.1109/4235.788491

Cited by 168 publications

(113 citation statements)

References 12 publications

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“…Lohn et al [LC99] thus represent a circuit as a set of chronologically executed operations, which finally construct a circuit. This approach is quite similar to what has been done by Ando et al [AII03], but is here explicitly named as variable length chromosome.…”

Section: State-of-the-art In Analog Synthesismentioning

confidence: 99%

FEATS: Framework for Explorative Analog Topology Synthesis

Meißner

Hedrich

2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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The presented work inside this thesis aims to raise the degree of automation in analog circuit design. Therefore, a framework was developed to provide the necessary mechanisms in order to carry out a fully automated analog circuit synthesis, i.e., the construction of an analog circuit fulfilling all previously defined (electrical) specifications.Nowadays, analog circuit design in general is a very time consuming process compared to a digital design flow. Due to its discrete nature, the digital design process is highly automated and thus very efficient compared to analog circuit design. In modern Very-Large-Scale integration (VLSI) circuits the analog parts are mostly just a small portion of the overall chip area. Although this small portion is known to consume a major part of the needed workforce. Paired with product cycles which constantly get shorter, the time needed to develop the analog parts of an integrated circuit (IC) becomes a determinant factor. Apart from this, the ongoing progress in semiconductor processing technologies promises more speed with less power consumption on smaller areas, forcing the IC developers to keep track with the technology nodes in order to maintain competitiveness. Analog circuitry exhibits the inherent property of being hard to reuse, as porting from one technology node to another imposes critical changes for operating conditions (e.g., supply voltage) -mostly leading to a full redesign for most of the analog modules. This productivity gap between digital and analog design resembles the primary motivation for this thesis.Due to the availability of commercial sizing tools, this work deliberately focuses on the construction of circuit topologies in distinction to parameter synthesis, which can be obtained with a dedicated sizing tool. The focus on circuit construction allows the development of a framework which allows a full design space exploration. This thesis describes the needed concepts and methods to realize a deterministic, explorative analog synthesis framework. Despite this, a reference implementation is presented, which demonstrates the applicability in current analog design flows. circuit (c) a circuit representing a physical realization circuits (C) an unordered set of circuits design space (DS) design space seen as crossproduct of P S and ST S devices (M ) an unordered set of devices equivalence class (eqcls) an unordered set of objects sharing the combination set of invariant properties equivalence classes (EQCLS(c)) set of equivalence classes associated with the circuit c graph (G) a representation of object vertices connected through edges ground (V GN D ) name of the reference net or simply ground hash (hash(x)) hash associated with object x integer (N) integer numbers invariant properties (EQP ROP S(x)) set of invariant properties associated with x invariant property (p) a property associated with a specific IV i invariants (IV) an unordered set of invariants label (L(x)) label associated with object x nets (N ) an unordered set of nets parameter space ...

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Section: State-of-the-art In Analog Synthesismentioning

confidence: 99%

FEATS: Framework for Explorative Analog Topology Synthesis

Meißner

Hedrich

2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…However, they did not specifically work on evolving robust circuits. Lohn and Colombano [15] proposed a linear representation approach to evolve analog circuits in which several lowpass filters were used as test problems. In another work, by Goh and Li [42], a genetic algorithm with a linear direct encoding approach is used to evolve lowpass and bandpass analog filters.…”

Section: Related Workmentioning

confidence: 99%

“…For each synthesis problem, three experiments are conducted: (a) evolutionary synthesis using GP without considering robustness criteria, (b) improvement in robustness of these evolved filters by tuning their parameters using a genetic algorithm (GA), and (c) evolution of robust filters (topological structure and parameters) using GP with a robustness criterion in the fitness function. These filter design problems are selected as they are perhaps the most popular problems in evolutionary synthesis research by either GA or GP [13][14][15].…”

Section: Introductionmentioning

confidence: 99%

A Novel Evolutionary Algorithm for Designing Robust Analog Filters

Zou

2018

Algorithms

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Designing robust circuits that withstand environmental perturbation and device degradation is critical for many applications. Traditional robust circuit design is mainly done by tuning parameters to improve system robustness. However, the topological structure of a system may set a limit on the robustness achievable through parameter tuning. This paper proposes a new evolutionary algorithm for robust design that exploits the open-ended topological search capability of genetic programming (GP) coupled with bond graph modeling. We applied our GP-based robust design (GPRD) algorithm to evolve robust lowpass and highpass analog filters. Compared with a traditional robust design approach based on a state-of-the-art real-parameter genetic algorithm (GA), our GPRD algorithm with a fitness criterion rewarding robustness, with respect to parameter perturbations, can evolve more robust filters than what was achieved through parameter tuning alone. We also find that inappropriate GA tuning may mislead the search process and that multiple-simulation and perturbed fitness evaluation methods for evolving robustness have complementary behaviors with no absolute advantage of one over the other.

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“…and Filter Design [15] GA A CD T/R/L/C Custom OFL Off-chip S Analog Circuit Synthesis [12] GP A CD R/L/C Custom OFL Off-chip S Character Recognition [31] GA D CD Gate Comm. OFL Off-chip S Clock Adjustment [27] GA D CT Gate Custom ONL Off-chip S Digital Filter Design [16] GA D CD Gate -OFL Off-chip S Gene Finding [39] GA D CD Gate Comm.…”

Section: Technology (Te) Technology For the Target Ehwmentioning

confidence: 99%

An Evolvable Hardware Tutorial

Tørresen

2004

Field Programmable Logic and Application

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Abstract. Evolvable Hardware (EHW) is a scheme -inspired by natural evolution, for automatic design of hardware systems. By exploring a large design search space, EHW may find solutions for a task, unsolvable, or more optimal than those found using traditional design methods. During evolution it is necessary to evaluate a large number of different circuits which is normally most efficiently undertaken in reconfigurable hardware. For digital design, FPGAs (Field Programmable Gate Arrays) are very applicable. Thus, this technology is applied in much of the work with evolvable hardware. The paper introduces EHW and outlines how it can be applied for hardware design of real-world applications. It continues by discussing the main problems and possible solutions. This includes improving the scalability of evolved systems. Promising features of EHW will be addressed as well, including run-time adaptable systems.

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A circuit representation technique for automated circuit design

Cited by 168 publications

References 12 publications

FEATS: Framework for Explorative Analog Topology Synthesis

FEATS: Framework for Explorative Analog Topology Synthesis

A Novel Evolutionary Algorithm for Designing Robust Analog Filters

An Evolvable Hardware Tutorial

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