A closed-form energy model for VLSI circuits under wide voltage scaling

Jain, Saurabh; Alioto, Massimo

doi:10.1109/icecs.2016.7841260

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“…Therefore, designing an SCL using this tool is almost impossible [13]. With regards to the manual characterization, the challenge is that we have to do many simulations to generate timing, power consumption, etc [14]. This way takes much time to design each logic cell.…”

Section: Introductionmentioning

confidence: 99%

A Novel Approach to Design a Process Design Kit Digital for CMOS 180nm Technology

Cong¹,

Le-Thanh²,

Bao³

et al. 2021

Adv. sci. technol. eng. syst. j.

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In this paper, a novel approach to design a Process Design Kit Digital for CMOS 180nm process is presented. This work proposes a detailed flow to design a PDK Digital using Ocean language, which is a vital element in the semi-custom design and applied in education purposes in universities in Vietnam. The PDK digital includes Standard Cell Library containing 47 standard cells and Wire-Load Model. The library is designed based on the CMOS 180nm process with a supply voltage of 1.8V.

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Section: Introductionmentioning

confidence: 99%