A CML GaAs 4Kb SRAM

Abstract

FOR THE APPLICATION of GaAs LSIs to the critical components of existing computer systems, compatibility to Si LSIs and a large load drive capability are indispensable. With these requirements in mind, a CML compatible GaAs 4Kb static RAM has been designed. The block diagram of this SRAM is shown in Figure 1. The design included Source Coupled FET Logic (SCFL)' for the peripheral circuit, because it was suitable for the adjustment of the supply voltages and the input/output levels to the CML level, as well as being able t o drive large loads. The memory cell, on the other hand, is composed of conventional E/D-DCFL circuitry.The SCFL has two diodes in series between the output electrode and ground, as shown in Figure 2. Because the diodes develop a constant potential drop, the controlled output swing can be expected even if there is some variation in the transistor characteristics, provided the voltage gain is sufficiently large.The reference voltage needed for the SCFLs X, Y decoder circuits was generated by a dummy circuit having almost the same circuit implementation as the ' O R logic part of the decoder circuit. These circuit contrivances, which can absorb some variation in the FET characteristics, are important from a practical point of view. The total 4Kb SRAM was designed by SPICE I1 simulation, to operate at supply voltages of -3.3V and -lV and to provide 0.5V output swing (VH = OV, VL = -0.5V) with 50fi output impedance. The FET transconductances used in the computer simulation are 170mS/ mm for E FET (vth = 0.2V), and 2OOmS/mm for D FET (Vth = -0.4V). The interconnect capacitance (75fF/mm) and the crossover capacitance (1fF) were also included in the simulation. The calculated performance of the device has shown that the address access time and the power dissipation are 0.97ns and 2.3W, respectively.The GaAs 4Kb SRAM was fabricated by using sidewallassisted closely-spaced electrode FET technology2, where the spacings between source and gate, drain and gate are extremely narrow, to reduce the parasitic series resistances. Separation is by very thin (0.25~) films prepared on both sides of the gate electrode. The threshold voltages and gms of the FETs have been measured: average values and the standard deviations are 0.34V (u = 0.035V) and 123mS/mm (a = 27mS/mm) for the E FET and -0.23V (a = 96mV) and 215mS/mm (0 = 42mS/mm) for the D FET. The specifications for the ion implantation used are: dosages, 1.4 x 1012cm--2 for the E FET and 3.2 x for the D GET and acceleration energy, 30keV for both cases.ductor Devices and Materials, IECE of Japan; 1981. 'Takada, T., et. al., 123, National Conference on Semi Con-Electrode Technology for High-speed GaAs LSIs", Extended Higashisaka, A., et. al., "Sidewall-Assisted Closely-Spaced Abstracts of the Conference on Solid State Devices and Materials. Tokyo, p. 69-72; 1983.Figures 3 and 4 are microphotographs of the chip and the memory cell, respectively. Chip size is 6.67mm x 6.61mm; the cell size is fj9p X 55/1 These sizes are relatively large, because conservative wirin...