A CMOS high-speed data recovery circuit using the matched delay sampling technique

Abstract

This paper presents a scheme and circuitry for demultiplexing and synchronizing high-speed serial data using the matched delay sampling technique. By simultaneously propagating data and clock signals through two di erent delay taps, the sampler achieves a very ne sampling resolution which is determined by the di erence between the data and clock delays. Thus, the sampler is capable of oversampling high speed data signals without the need of a high-speed clock and it could be used in a data recovery circuit. A data recovery circuit using the matched delay sampling technique has been designed and fabricated in 1.2 m CMOS technology. The chip has been tested at 417Mb/s (2.4ns NRZ) input data and demultiplexes serial input data into four 104Mb/s output streams with 800mW power consumption at 4V power supply. While recovering data, the sampling clock running at 1/4 of the data frequency is phase-tracking with the input data based on information extracted from a digital phase control circuit.