A CMOS RF power detector for an Automatic Impedance Matching System

Abstract

This paper presents the design of a CMOS RF RMS power detector for an Automatic Impedance Matching System. The power detector requirements for this application, in terms of dynamic range, resolution, settling time and power consumption, are met by distributing the dynamic range over three power detection units. The appropriate unit is dynamically selected based on the input power range. The output of the detector is digital and linear-in-decibel. The selectors and detection units have been designed in 0.13-μm CMOS technology. Circuit-level simulation results show a dynamic range of 27 dB for input frequencies extending from 800 MHz to 8.5 GHz. The sensitivity of the power detector is −27 dBm, the settling time is less than 12 μs and the power consumption is 1.2 mW.

The Design of a Wide-Dynamic-Range and High-Linearity RMS Power Detector for mm-Wave Applications in 65 nm CMOS

“…A power detector (PD) plays a vital role in testing and calibrating power that is received or transmitted, and it is widely used in wireless communication systems or radar systems [1][2][3][4][5][6][7][8][9][10]. As shown in Figure 1, the power detector is used to test or calibrate the output power of the power amplifier (PA) or the gain of the low noise amplifier (LNA) [2,4].…”

“…However, it requires an extra bias circuit module and algorithm to control the programmable voltage bias circuit, and it detects the radio frequency signal peak amplitude rather than the RMS value. A dynamic range extended method based on a digital control multiple power detector unit was illustrated in [9]. It requires an extra ADC and finite state machine to control the detection unit.…”