A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT

Wang, Zeke; Li, Xue; He, Bingsheng; Yu, Feng

doi:10.1109/tvlsi.2014.2319335

Cited by 66 publications

(38 citation statements)

References 18 publications

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“…In [21] a combined SDF-SDF radix-2 single-stream pipeline FFT architecture was proposed. Also this architecture uses time-multiplexing and splitting of the complex samples to reduce the number of adders/subtracters and multipliers needed.…”

Section: Comparison With Earlier Proposed Architecturesmentioning

confidence: 99%

“…In [10], the serial commutator (SC) FFT was proposed by Garrido et al The SC architecture is similar to those proposed in [3,21] in the sense that minimal number of adders/subtracters is achieved by time-sharing over the realimaginary dimension. Note, that the number of memory slots for the SC FFT differs between what is reported in [10].…”

Section: Comparison With Earlier Proposed Architecturesmentioning

confidence: 99%

“…Since then several single-stream FFT architectures have been suggested [2,3,6,10,18,21,24]. Some decades later, a major milestone in this field came with the introduction of the radix-2 2 algorithm [14].…”

Section: Introductionmentioning

confidence: 99%

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SFF—The Single-Stream FPGA-Optimized Feedforward FFT Hardware Architecture

Ingemarsson

Gustafsson

2018

J Sign Process Syst

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In this paper, a fast Fourier transform (FFT) hardware architecture optimized for field-programmable gate-arrays (FPGAs) is proposed. We refer to this as the single-stream FPGA-optimized feedforward (SFF) architecture. By using a stage that trades adders for shift registers as compared with the single-path delay feedback (SDF) architecture the efficient implementation of short shift registers in Xilinx FPGAs can be exploited. Moreover, this stage can be combined with ordinary or optimized SDF stages such that adders are only traded for shift registers when beneficial. The resulting structures are well-suited for FPGA implementation, especially when efficient implementation of short shift registers is available. This holds for at least contemporary Xilinx FPGAs. The results show that the proposed architectures improve on the current state of the art.

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Section: Comparison With Earlier Proposed Architecturesmentioning

confidence: 99%

Section: Comparison With Earlier Proposed Architecturesmentioning

confidence: 99%

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SFF—The Single-Stream FPGA-Optimized Feedforward FFT Hardware Architecture

Ingemarsson

Gustafsson

2018

J Sign Process Syst

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Section: …………………………………………………………………………………………………… Introduction:-mentioning

confidence: 99%

“…The SDF concept extended to radix 2 to radix 2 k [4][5][6]. The high throughput requirements of communication services encouraged to multipath delay commutators [7] and multipath delay feedback (MDF) [8].The MDF structures are formed using multiple interconnected SDFs. The MDF scheme is utilized in various applications due to its efficient memory usage, but suffers from arithmetic resource utilization and it is rectified in M 2 DF architecture [9], which utilizes the folding transformation technique for the significant reduction of arithmetic resources.…”

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confidence: 99%

Tunable Mixed Decimation Multipath Delay Feedback for Radix 2k FFT

Bhavani¹,

Raju²

2018

IJAR

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The Decimation Multipath Delay Feedback (M 2 DF) is a technique for the radix 2 k FFT, which eliminates the stand by time of arithmetic modules in computing units. In this paper tunable M 2 DF architecture is proposed. In this, tunable arithmetic units are utilized in place of conventional arithmetic units to overcome the under utilization of arithmetic units in conventional M 2 DF architecture. The results show that, the tunable M 2 DF technique utilizes the lesser number of LUTs and slice registers than the conventional M 2 DF technique. In addition, the proposed technique having advantage of high throughput with reduced delay and area compared with conventional M 2 DF.Copy Right, IJAR, 2018,. All rights reserved. …………………………………………………………………………………………………….... Introduction:-Fast Fourier Transform (FFT) is mostly used algorithm for Discrete Fourier Transform computation in the field of signal processing. The area efficient and high performance FFT implementation throws a challenge on the designers. Hardware designers are putting effort to design effectual architectures for the computation of the FFT to meet required specifications and real-time fulfillment of present applications. Various techniques have proposed over the years to tradeoff the area and performance of the FFT. Pipelined architectures [1] are extensively used because they will achieve more throughputs and small latencies relevant for today's applications to achieve small area and to dissipate less power. The single path delay commutators (SDC) [2] are the most popular technique in the serial input and serial output scenarios. Single path delay feedback (SDF) architecture is proposed to reduce the memory banks in the pipelines [3]. The SDF concept extended to radix 2 to radix 2 k [4][5][6]. The high throughput requirements of communication services encouraged to multipath delay commutators [7] and multipath delay feedback (MDF) [8].The MDF structures are formed using multiple interconnected SDFs. The MDF scheme is utilized in various applications due to its efficient memory usage, but suffers from arithmetic resource utilization and it is rectified in M 2 DF architecture [9], which utilizes the folding transformation technique for the significant reduction of arithmetic resources.In this work, tunable M 2 DF architecture is proposed to further reduce the arithmetic operations in terms of number of LUTs and registers.Construction of M 2 DF Architecture:-Design of parallel radix-2 k FFT processor based on folding transformations to derive the folding matrices of DIF and DIT of SDF structures. The pipelined structure is rescheduled by incorporating DIF blocks into DIT blocks to form

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