A Compact, Low-Phase Noise Fractional-N PLL for Global Navigation Receiver

Kharalkar, Ajinkya; Pancholi, Mukul; Kanchetla, Vijaya Kumar; Khade, Aniruddha; Khyalia, Santosh Kumar; Hameed, Syed; Zele, Rajesh

doi:10.1109/newcas50681.2021.9462747

Cited by 8 publications

(3 citation statements)

References 8 publications

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“…This work achieved the best figure of merit (FoM) of 171.3 dBc/Hz for the S-band compared to other works related to GPS applications. The FoM of the proposed wideband PLL was better than [18]. The reference spur in [26] was better but it came at the cost of an inferior PN, which is reflected in its FoM.…”

Section: Measurement Resultsmentioning

confidence: 90%

“…There are single voltage-controlled oscillator (VCO) [15], multiple VCO PLLs' [16], and rotatory traveling wave oscillator [17] architectures described in the literature. The most recent research covers both bands with a single broadband voltage-controlled oscillator (VCO) [18]. To achieve this, the PLL must operate at a reasonable power consumption with an acceptable quality factor (Q) and have stability throughout the whole range.…”

Section: Overview Of Irnss Pllmentioning

confidence: 99%

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A Simplified Gm − C Filter Technique for Reference Spur Reduction in Phase-Locked Loop

Chary,

Shaik Peerla,

Dutta

2024

JLPEA

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This paper presents a wideband approach for L5 and S-band integer-N phase-locked loop (PLL) targeting Indian Regional Navigation Satellite System (IRNSS) applications. A reference spur reduction technique using a Gm−C filter is proposed. The reference spur is improved by 7 dB when compared with one without any Gm−C filter. The wideband integer-N PLL is designed and fabricated in UMC 65-nm CMOS process. The Gm−C filter block consumes 200 μA current. The wideband voltage-controlled oscillator (VCO) oscillates from 1.6 GHz to 3.2 GHz having a tuning range (TR) of 40%, achieving a best and worst phase noise of ≈−122 dBc/Hz and ≈−116 dBc/Hz at a 1 MHz offset, respectively.

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Section: Measurement Resultsmentioning

confidence: 90%

Section: Overview Of Irnss Pllmentioning

confidence: 99%

A Simplified Gm − C Filter Technique for Reference Spur Reduction in Phase-Locked Loop

Chary,

Shaik Peerla,

Dutta

2024

JLPEA

View full text Add to dashboard Cite

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“…It allows to share the required components like frequency synthesizers which further reduces area overhead and increases the level of integration. The single low noise frequency synthesizer that can provide LO signals for L1, L2, L5 and S bands is proposed in this paper [53]. In various literature, different sort of frequency planning scheme is discussed.…”

Section: A Frequency Planningmentioning

confidence: 99%

Advanced System Analysis and Survey on the GPS Receiver Front End

Kumari

Bhatt

2022

IEEE Access

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A fully integrated GPS receiver system can enable unique system capabilities by synthesizing both receiver front end and baseband on the same chip, leading to lower area overhead and higher integration. A review on the GPS receiver system that focuses on front end design is presented in the paper. The first section discusses the various global navigation satellite system (GNSS), followed by the GPS working section. Afterwards, the paper discusses the previous works on the GPS receiver front end design. It provides a detailed survey and classification of various receiver architecture, including the LNA, mixer, filter, and ADC topologies. Besides, several image rejection techniques are presented for more than 50 GPS receivers. The various performance parameters of the GPS receiver front end in the literature are presented with the graphical view in the state-of-the-art discussion section. This literature survey provides the most extensive compilation to date of the various topologies, techniques and explains their implementation in the GPS receiver system. A new figure of merit that includes all the system parameters is proposed. The FOM can be an excellent reference to enhance the research work in the field of GPS receivers. In the end, the paper describes the possible research scope and challenges associated with the design of the GPS receiver front end.INDEX TERMS global navigation satellite system (GNSS), image rejection, RF front end, sensitivity, spurious free dynamic range (SFDR), wireless communication.

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A 5.12-GHz LC-based phase-locked loop for silicon pixel readouts of high-energy physics

Wei

Zhang

et al. 2022

NUCL SCI TECH

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A Compact, Low-Phase Noise Fractional-N PLL for Global Navigation Receiver

Cited by 8 publications

References 8 publications

A Simplified Gm − C Filter Technique for Reference Spur Reduction in Phase-Locked Loop

A Simplified Gm − C Filter Technique for Reference Spur Reduction in Phase-Locked Loop

Advanced System Analysis and Survey on the GPS Receiver Front End

A 5.12-GHz LC-based phase-locked loop for silicon pixel readouts of high-energy physics

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