A Comparison of Single-Buffer and Double-Buffer Design in a Systolic Array Generator

Abstract

In application fields such as face recognition and image recognition using deep learning, more convolution operations are required for the increasing amount of data. Therefore, the use of systolic array acceleration is becoming a key technology trend to accelerate the development of deep learning applications. In previous designs, most of the systolic array used single-buffer or double-buffer structures, but most of them did not compare the difference between the two in detail. This work designs and implements a three-level systolic array generator, which can be configured in single-buffer or double-buffer modes. We also program the generated systolic array accelerator on Nexys-Vedio FPGA to explore the performance and overhead of single-buffer and double-buffer structure modes. The results show that the throughput of the double-buffer structure is increased by nearly 3 × compared to the single-buffer structure while only brings an additional 28% power consumption and 25% area overhead under the SIMC 130nm technology. And compared with the previous work, the proposed systolic array generator reduces power consumption by 75% and area overhead by 34% with almost no loss in performance.