A Comprehensive Analysis of Different SRAM Cell Topologies in 7-nm FinFET Technology

Abstract

This article aims to provide a wide comparative analysis of different SRAM cells in 7nm FinFET Technology. Due to various limitations of the CMOS device in nanotechnology, FinFET is one of the trending choices for memory designers which can improve the stability and minimize the Short Channel Effects of the CMOS. Here, performance metrics of these SRAM cells like the stability, access time, power have been measured at a supply voltage range of 0.2 V to 0.5 V. The layout of the existing cells has been designed and compared in which the ST12T consumes the maximum area. The simulated results inferred that the ST11T SRAM cell offers the highest RSNM and the minimum dynamic and leakage power amongst all the SRAM cells. Moreover, ST12T SRAM cell has the highest WSNM in comparison to other SRAM cells. An electrical quality metric has been utilized, which displays the superiority of the ST12T SRAM cell amongst all the considered SRAM cells in this article.