A comprehensive study of degradation behavior of select transistors in the Charge Trap Flash memories

Abstract

The local electron trapping in the select transistors used in the Charge Trap Flash (CTF) NAND was analyzed in depth for the first time in terms of operation conditions and gate spacer process. In this work, we examined the mechanism of swing degradation in the select transistors with TANOS (TaN-Al2O3-Si3N4-SiO2-Si) structure due to repetitive program/erase [P/E] operation. The swing degradation can be explained by the local electron trapping induced from electric field between select transistors and neighboring transistors. The local electron trapping in select transistors are well correlated to the saturation of threshold voltage in the erased cells. The erase Vth saturation appears to be caused by unfavorable backward tunneling of electrons from gate to the trap layer. The degradation in the select transistor is perfectly solved by decreasing the electric field during erase operation and keeping an appropriate distance between select transistors and neighboring transistors.