A Cryogenic 8-Bit 32 MS/s SAR ADC Operating down to 4.2 K

Abstract

This paper presents a cryogenic 8-bit 32 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) which operates down to 4.2 K. This work uses a modified liquid helium temperature (LHT) SMIC 0.18 μm CMOS technology to support the post-layout simulation. The proposed architecture adopts an offset-promoted dynamic comparator, waveform shaping circuit and true single-phase clock (TSPC) based sar logic circuit to achieve high realizing frequency and low power dissipation. At 1.8-V supply, 1.7 V input amplitude and 32 MS/s sampling frequency, the ADC achieves a power consumption of 2.4 mW and a signal-to-noise and distortion ratio (SNDR) of 47.7 dB, obtaining a figure of merit (FOM) of 378 fJ/conversion-step. The layout area of the ADC is about 0.253 mm2.

A Reconfigurable Hybrid ADC Using a Jump Search Algorithm

“…Among recently researched ADCs [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20], various hybrid structures [11][12][13][14][15][16][17][18][19] are being explored. However, the SAR ADC architecture is required due to the low power consumption, bandwidth, and resolution for biomedical signal processing.…”