A design-flow for high-level synthesis and resource estimation of reconfigurable architectures

Abstract

Field Programmable Gate Arrays (FP-GAs), due to their programmability, have become a popular design choice for control and processing blocks of an embedded system. However, this flexibility makes them larger, slower and less power-efficient than Application Specific Integrated Circuits (ASICs) and hinders their use in low-area and low-power applications. On the other hand, ASICs have their inherent drawbacks like lack of programmability and inflexibility. The solution is reconfigurable architectures that have improved flexibility over ASICs and better resource utilization than FPGAs. However, designing a reconfigurable architecture is a daunting task in itself due to lack of high-level design-flow support. This paper proposes an automated design-flow for system-level synthesis and resource estimation for generic as well as custom reconfigurable architectures. The experimental results show that the generated reconfigurable architectures are 79% more area and 76% more power efficient than generic academic FPGA-based implementations.

A framework for high-level simulation and optimization of fine-grained reconfigurable architectures

“…These results not only establish the applicability of our framework to a wide variety of applications, but also reinforce the previously published results related to resource and power comparison of FPGAs and ASIFs. 8,9 In addition, all these area and power savings are obtained with much less design effort thanks to our automated design-flow that lets us work at a higher abstraction level of the ANSI-C language.…”

“…Moreover, these results are consistent for both control-oriented and compute-intensive applications, and demonstrate similar resource savings across homogeneous and heterogeneous domains that have already been reported in the literature. 8,9 Figures 10–12 give a quick visual overview of the results that are detailed in Tables 4 and 8–10.…”

“…In this article, we propose a generic high-level framework that can be used for automated simulation, optimization, and resource (power and area) estimation of a digital system that will eventually be implemented on a target fine-grained reconfigurable architecture. The work presented here is an extension of our previous work, 8 where we proposed a design-flow that targets only homogeneous fine-grained reconfigurable architectures. In the current version, we extend the exploration environment to support heterogeneous fine-grained architectures as well.…”