A Differential-Ramp Based 65 dB-Linear VGA Technique in 65 nm CMOS

Elwan, H.O.; Tekin, Ahmet; Pedrotti, Kenneth D.

doi:10.1109/jssc.2009.2021446

Cited by 94 publications

(42 citation statements)

References 16 publications

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“…The PMA is followed by a two-stage voltage-rampbased rail-to-rail input and output swing variable gain amplifier (VGA) with linear-in-dB gain characteristics [6]. Many CMOS VGA designs proposed in the literature report very linear operation by controlling the VGA gain in steps [7,12].…”

Section: Baseband Architecturementioning

confidence: 99%

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A universal low-noise analog receiver baseband in 65-nm CMOS

Tekin

Elwan²,

Pedrotti

2010

Analog Integr Circ Sig Process

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In this paper, a novel universal receiver baseband approach is introduced. The chain includes a postmixer noise shaping blocker pre-filter, a programmable-gain post mixer amplifier (PMA) with blocker suppression, a differential ramp-based novel linear-in-dB variable gain amplifier and a Sallen-Key output buffer. The 1.2-V chain is implemented in a 65-nm CMOS process, occupying a die area of 0.45 mm 2 . The total power consumption of the baseband chain is 11.5 mW. The device can be tuned across a bandwidth of 700-KHz to 5.2-MHz with 20 kHz resolution and is tested for two distinct mobile-TV applications; integrated services digital broadcasting-terrestrial ISDB-T (3-segment f c = 700 kHz) and digital video broadcastingterrestrial/handheld (DVB-T/H f c = 3.8 MHz). The measured IIP3 of the whole chain for the adjacent blocker channel is 24.2 and 24 dBm for the ISDB-T and DVB-T/H modes, respectively. The measured input-referred noise density is 10.5 nV/sqrtHz in DVB-T/H mode and 14.5 nV/ sqrtHz in ISDB-T mode.

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Section: Baseband Architecturementioning

confidence: 99%

“…Recently, many high performance direct conversion receiver (DCR) and low-IF receiver circuits have been reported [2][3][4][5][6][7][8][9][10][11]. Most of these designs tailor the technology and the classical circuit techniques to achieve good performance for a given application.…”

Section: Introductionmentioning

confidence: 99%

A universal low-noise analog receiver baseband in 65-nm CMOS

Tekin

Elwan²,

Pedrotti

2010

Analog Integr Circ Sig Process

Self Cite

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“…Various techniques to control the gain of a VGA in CMOS technologies include varying: (1) the effective trans-conductance of input stage [1,15,16], (2) the load resistance, (3) and the feedback network resistances of a high gain amplifier [17]. Detailed classification of VGAs may be found in [17][18][19].…”

Section: Introductionmentioning

confidence: 99%

“…For example, to overcome the limited tuning range and non-linearity problems related to feedback tuning technique, a differential ramp based technique was introduced in [17]; and, to improve the linearity performance of a source degenerated VGA, a load degeneration technique was introduced in [2]. Although the reported works present some merits, in most cases, a few of VGA specifications have been improved.…”

Section: Introductionmentioning

confidence: 99%

A 0.74 mW, linear-in-dB, constant bandwidth, variable gain amplifier based on zero-pole repositioning technique

Baghtash

2015

Analog Integr Circ Sig Process

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A zero-pole repositioning based variable gain amplifier is presented in this paper. The operational principle of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by simulation in TSMC 0.18 lm standard CMOS technology. Owing to the cutting-edge structure, the proposed circuit demonstrates a very low power consumption of 0.74 mW and a wide tuning range of 83 dB. The proposed structure benefits from linear-in-dB and constant bandwidth specifications. The linear-in-dB gain range of structure is about 70 dB. The structure draws about 413 lA from 1.8 V power supply and regarding this low power consumption, it shows a lower and upper 3-dB cutoff frequencies of 8 Hz and 8.1 MHz, respectively. Process and temperature variation analysis of the circuit is also investigated through Monte Carlo and corner case analysis in order to verify the well-robustness of the structure. The transient sinusoidal response analysis is also done to verify the proposed VGA's stability.

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“…The increased popularity of 2.4 GHz ISM band devices for a different end user and corporate applications such as RFID, Bluetooth, Zigbee and Wi-Fi devices, non-contacting medical instruments, sensors etc., in the recent years, has raised the demand for small power and less off-chip components which tends to achieve integration of multiple transmitter/receiver chains on the same die [1][2][3]. As a result, highly integrated and area efficient designs are the current trends of IC design.…”

Section: Introductionmentioning

confidence: 99%

Design of a nanoswitch in 130 nm CMOS technology for 2.4 GHz wireless terminals

Bhuiyan¹,

Reaz²,

Jalil³

et al. 2014

Bulletin of the Polish Academy of Sciences Technical Sciences

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Abstract. This paper proposes a transmit/receive (T/R) nanoswitch in 130 nm CMOS technology for 2.4 GHz ISM band transceivers. It exhibits 1.03-dB insertion loss, 27.57-dB isolation and a power handling capacity (P1 dB) of 36.2-dBm. It dissipates only 6.87 µW power for 1.8/0 V control voltages and is capable of switching in 416.61 ps. Besides insertion loss and isolation of the nanoswitch is found to vary by 0.1 dB and 0.9 dB, respectively for a temperature change of 125• C. Only the transistor W/L optimization and resistive body floating technique is used for such lucrative performances. Besides absence of bulky inductors and capacitors in the schematic circuit help to attain the smallest chip area of 0.0071 mm 2 which is the lowest ever reported in this frequency band. Therefore, simplicity and low chip area of the circuit trim down the cost of fabrication without compromising the performance issue.

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A Differential-Ramp Based 65 dB-Linear VGA Technique in 65 nm CMOS

Cited by 94 publications

References 16 publications

A universal low-noise analog receiver baseband in 65-nm CMOS

A universal low-noise analog receiver baseband in 65-nm CMOS

A 0.74 mW, linear-in-dB, constant bandwidth, variable gain amplifier based on zero-pole repositioning technique

Design of a nanoswitch in 130 nm CMOS technology for 2.4 GHz wireless terminals

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