A digital background calibration technique for SAR ADC based on capacitor swapping

Abstract

A digital background calibration technique that compensates for capacitor mismatches is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in the SAR ADC based on tri-level switching. The termination capacitor in the digital-to-analog converter is considered as a reference capacitor and the digital weights of all other unit capacitors are corrected with respect to the reference capacitor. Behavior simulation is performed to verify the proposed calibration technique by using a 12-bit SAR ADC with 3% random capacitor mismatch. The simulation result shows that the signal-to-noise and distortion ratio is improved from 57.1 dB to 72.0 dB and the spurious free dynamic range is improved from 62.0 dB to 82.6 dB.