ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187)
DOI: 10.1109/iscas.1998.698889
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A digital frequency modulator circuit for a dual-mode cellular telephone

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Cited by 3 publications
(2 citation statements)
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“…Some of these have laid stress on reducing the distortion effects of quantization noise, which occurs due to the bit resolution at the input and output of the DDFS [1]. Some of them have discussed the area optimization and low-power consumption [2][3][4] as main objective. In the present work, one high-speed, low-power, and reduced-area digital FM modulator has been implemented in the FPGA device to support the audio broadcasting system in software-defined radio (SDR) system.…”
Section: Introductionmentioning
confidence: 99%
“…Some of these have laid stress on reducing the distortion effects of quantization noise, which occurs due to the bit resolution at the input and output of the DDFS [1]. Some of them have discussed the area optimization and low-power consumption [2][3][4] as main objective. In the present work, one high-speed, low-power, and reduced-area digital FM modulator has been implemented in the FPGA device to support the audio broadcasting system in software-defined radio (SDR) system.…”
Section: Introductionmentioning
confidence: 99%
“…Some works have laid stress on reducing the distortion effects of quantisation noise, which occurs owing to the difference in bit resolutions at the input and output of the DDFS (Twelves and Kikkert, 1996). Area optimisation and low-power consumption (Lathi and Niemisto, 1998;Unsikartano et al, 1999;Twelves and Kikkert, 1997) have been the main objectives. In this work, a low-power, low-area and high-speed programmable modulator capable of performing both GMSK and FM methods has been implemented in FPGA to support the different standards as listed in Table 1 in SDR system, whereas Table 2 indicates the different parameters for the GSM and DECT mobile protocols.…”
Section: Introductionmentioning
confidence: 99%