A discrete-time analog signal processor for disk read channels

Abstract

A signal processor incorporates equalization, clock recovery, AGC, and peak detection for waveforms in the disk read channel, and operates up to a 40MHz clock rate. The 2pm CMOS IC uses precision analog MOS signal processing implemented with scaled-down unit cells, and dissipates 500mW from a 5V power supply.

IoT receiver techniques: on filtering, power consumption and phase noise

“…Several approaches still used the direct implementation architecture (Fig. 2.1a) [40][41][42][43][44][45][46][47][48][49][50][51] -where the delay line is implemented using switch-capacitor amplifiers [52] -similar to the charge transfer device analog FIR 2.3. Analog FIR Filters Prior Art Figure 2.9: Analog FIR filter with sub-sampled output as pre-filter of a SAR ADC [68].…”

“…Analog FIR techniques can also be implemented as equalizers [45-48, 57, 59-62, 117]. In the 1990s, the analog FIR equalizer was a popular research topic for the read-out circuits of magnetic storage devices [45,46,48,[57][58][59][60][61][62].…”