A double-quadrature down-conversion mixer in 0.18 &amp;#x03BC;m SiGe BiCMOS process

Yan, Jun; Lim, Kok Meng; Gu, Jianlan; Wang, Keping; Lim, Wei Meng; Ma, Kaixue; Yeo, Kiat Seng

doi:10.1109/isocc.2011.6138756

Cited by 4 publications

(2 citation statements)

References 11 publications

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“…This paper has presented the design of a LP integrated quadrature demodulator along with a frequency divider. It has been shown that employing gate inductors for the differential transconductance stage of the mixer not only enhances the VCG, but also lowers the transconductor's noise contribution second only to Reference [8], but with a comparatively superior performance in terms of gain and NF with lower power dissipation.…”

Section: Discussionmentioning

confidence: 99%

A low power, low noise figure quadrature demodulator for a 60 GHz receiver in 65-nm CMOS technology

Amin

Wang

et al. 2015

J. Semicond.

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This paper presents the design of a low power (LP) and a low noise figure (NF) quadrature demodulator with an on-chip frequency divider for quadrature local oscillator (LO) signal generation. The transconductance stage of the mixer is implemented by an AC-coupled self-bias current reuse topology. On-chip series inductors are employed at the gate terminals of the differential input transconductance stage to improve the voltage gain by enhancing the effective transconductance. The chip is implemented in 65-nm LP CMOS technology. The demodulator is designed for an input radio frequency (RF) band ranging from 10.25 to 13.75 GHz. A fixed LO frequency of 12 GHz down-converts the RF band to an intermediate frequency (IF) band ranging from DC to 1.75 GHz. From 10 MHz to 1.75 GHz the demodulator achieves a voltage conversion gain (VCG) ranging from 14.2 to 13.2 dB, and a minimum single-sideband NF (SSB-NF) of 9 dB. The measured third-order input intercept point (IIP3) is −3.3 dBm for a two-tone test frequency spacing of 1 MHz. The mixer alone draws a current of only 2.5 mA, whereas the complete demodulator draws a current of 7.18 mA from a 1.2 V supply. The measurement results for a frequency divider, which was fabricated individually, prior to being integrated with the quadrature demodulator, in 65-nm LP CMOS technology, are also presented in this paper.

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Section: Discussionmentioning

confidence: 99%

A low power, low noise figure quadrature demodulator for a 60 GHz receiver in 65-nm CMOS technology

Amin

Wang

et al. 2015

J. Semicond.

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“…Gilbert mixer is quite common among SDR receiver architectures as they can provide high bandwidth and broadband performance without degradation in the performance parameters [ 31 ]. Several mixer designs have been discussed in [ 32 , 33 , 34 , 35 , 36 , 37 ]. As in [ 38 ], improved Gilbert mixer design is proposed that attains reasonable CG and high port isolation while operating within a wideband.…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of a Reconfigurable Gilbert Mixer for Software-Defined Radios

Mehta

Donelli

2021

Sensors

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A reconfigurable gm-boosted, image-rejected downconversion mixer is presented in this paper using the SiGe 8 HP technology. The proposed mixer operates within 0.9–13.5 GHz that is suitable for software-defined radio applications. The conversion mixer comprises of resistive biased radio frequency (RF) section, double balanced Gilbert cell mixer core sections divided as per I and Q stages for image-rejection purpose, inductively peaked gm-boosting section and tunable filter section, respectively. In comparison to previous works in the scientific literature, the design shows enhanced conversion gain (CG), noise figure (NF), and image-rejection ratio (IRR). For the entire band of operation, the mixer attains a good return loss |S11| of <−10 dB. Additionally, the design accomplishes an excellent CG of 22 dB, NF of 2.5 dB, and an image-rejection ratio of 30.2 dB at maximum frequency. Finally, a third-order intercept point (IP3) of −3.28 dBm and 1 dB compression point (CP1) of −13 dBm, respectively, shows moderate linearity performance.

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A Low Noise Image-Rejection Gilbert Mixer for Software Defined Radios

Mehta

Aneja

2020

2020 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)

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A double-quadrature down-conversion mixer in 0.18 μm SiGe BiCMOS process

Cited by 4 publications

References 11 publications

A low power, low noise figure quadrature demodulator for a 60 GHz receiver in 65-nm CMOS technology

A low power, low noise figure quadrature demodulator for a 60 GHz receiver in 65-nm CMOS technology

Design and Analysis of a Reconfigurable Gilbert Mixer for Software-Defined Radios

A Low Noise Image-Rejection Gilbert Mixer for Software Defined Radios

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