A DSP based H.264/SVCdecoder for a multimedia terminal

Pescador, F.; Samper, David; Raulet, Mickaël; Juárez, E.; Sanz, C.

doi:10.1109/tce.2011.5955211

Cited by 9 publications

(2 citation statements)

References 8 publications

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“…This optimizes IICT to a great extent since default 8×8 IICT will involve unnecessary multiplications and additions for the zero valued coefficients. In order to further to increase the decoding performance, a novel deblocking filer technique which uses only the internal memory proposed in [10] is implemented in our study. Use of Memory.…”

Section: Advanced Engineering Forum Vols 6-7mentioning

confidence: 99%

A Real-Time H.264 BP Decoder Based on ADSP-BF548

Tung

Wang

Jhuang

et al. 2012

AEF

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In this paper, we propose an embedded real-time H.264 Baseline Profile (BP) decoder based on ADSP-BF548 Blackfin processor. In order to achieve the real-time requirement of H.264 decoding, we modify and optimize the decoding modules and codes, respectively. Firstly, we analyze the number of operations for various modules using assembly code, and then use direct memory access (DMA) to carry out the parallelism between algorithm execution and data movement. Finally, we make use of two buffer groups (BG) as parallel decoding mechanism of broadcast transformation. Experimental results demonstrate that the play rate can reach above 25 fps as using QCIF video. According to some tests, a real-time H.264 BP decoding can be achieved with a 600 MHz DSP.

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Section: Advanced Engineering Forum Vols 6-7mentioning

confidence: 99%

A Real-Time H.264 BP Decoder Based on ADSP-BF548

Tung

Wang

Jhuang

et al. 2012

AEF

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“…Previous standard implementation: Authors in [4]suggested a DSP-based video decoder implementation compliant to H.264/SVC standard, improving the initial version performance about 40% within performance optimizations and reaching real-time for CIF sequences. Moreover, in [5], a multi-DSP based video decoder was accomplished in accordance with the H.264/SVC standard.…”

mentioning

confidence: 99%

DSP TMS320C6678 Based SHVC Encoder Implementation and its Optimization

Wali¹,

Kessentini²,

Ayed³

et al. 2022

IJRTE

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The programmable processors newest technologies, as for example the multicore Digital Signal Processors (DSP), offer a promising solution for overcoming the complexity of the real time video encoding application. In this paper, the SHVC video encoder was effectively implemented just on a single core among the eight cores of TMS320C6678 DSP for a Common Intermediate Format (CIF)input video sequence resolution(352x288). Performance optimization of the SHVC encoder had reached up 41% compared to its reference software enabling a real-time implementation of the SHVC encoder for CIF input videos sequence resolution. The proposed SHVC implementation was carried out on different quantization parameters (QP). Several experimental tests had proved our performance achievement for real-time encoding on TMS320C6678.

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