A Dynamically Reconfigurable Video Compression Scheme Using FPGAs with Coarse‐grain Parallelism

Abstract

A dynamically reconfigurable scheme for video encoder to switch among many different applications is presented. The scheme is suitable for FPGA implementation and conforms to JPEG, MPEG-1, MPEG-2, and H.263 standards. The scheme has emerged as an efficient and cost-effective solution for video compression as a result of innovative design using well-partitioned algorithms, highly pipelined architecture and coarse-grain parallelism. The reconfiguration time of the video encoder is less than 320 μs while switching from one standard to another. Although the dynamic reconfiguration scheme is presented for a video encoder, the same design methodology may be applied effectively for any other application.