A Fast Equation Free Iterative Approach to Analog Circuit Sizing

Abstract

A fast equation free iterative approach for sizing of analog circuit is proposed. Equation based sizing approach has been popular as it removes time consuming simulation effort. If equations are cast in posynomial inequality format, a special optimization technique called geometric programming (GP) can be deployed. The advantage of formulating the problem in GP form is that, it ensures global optimality and can return the final design point instantly even in the presence of hundreds of equation and thousands of variable. But main limitation comes in deriving performance equations in posynomial inequality format. In this context, we develop one novel methodology for fast sizing of analog circuit. This method does not require any such performance expressions. It is based on the meaningful presentation of only device constraints. Infeasibility is handled iteratively making suitable changes on those constraints. Due to the simplicity of formulation, fully automated flow is achieved.