A Fast Quantum Computer Simulator Based on Register Reordering

Abstract

SUMMARY Quantum computer simulators play an important role when we evaluate quantum algorithms. Quantum computation can be regarded as parallel computation in some sense, and thus, it is suitable to implement a simulator on hardware that can process a lot of operations in parallel. In this paper, we propose a hardware quantum computer simulator. The proposed simulator is based on the register reordering method that shifts and swaps registers containing probability amplitudes so that the probability amplitudes of target basis states can be quickly selected. This reduces the number of large multiplexers and improves clock frequency. We implement the simulator on an FPGA. Experiments show that the proposed simulator has scalability in terms of the number of quantum bits, and can simulate quantum algorithms faster than software simulators.

A hardware architecture for the Walsh–Hadamard transform toward fast simulation of quantum algorithms

“…For fast simulation of quantum computers, many simulation methods have been investigated intensively (Aminian et al 2008;De Raedt et al 2007;Frank et al 2009a, b;Fujishima 2003;Gutierrez et al 2008a, b;Khalid et al 2004;Niwa et al 2002;Obenland and Despain 1998;O'uchi et al 2002;Patz 2003;Shibata et al 2010;Tabakin and Juliá-Díaz 2009;Viamontes et al 2003Viamontes et al , 2005. Some of them implement the simulator on an LSI (Aminian et al 2008;Fujishima 2003;Khalid et al 2004;O'uchi et al 2002). Hardware implementation is considered to be suitable for tasks that run in parallel.…”

“…Quantum algorithms are often represented by quantum circuits. In Khalid et al (2004), an FPGA-based quantum circuit emulator is proposed. For each quantum gate, the corresponding classical sub-circuit that emulates the gate is implemented on the emulator.…”

“…By reconfiguring the sub-circuit, they constructed an efficient emulator. In Aminian et al (2008), it is shown that by adding several quantum circuit primitives to those in Khalid et al (2004), a lot of quantum algorithms can be simulated quickly and the size of the emulator circuit can be decreased. In Frank et al (2009a, b), a space efficient quantum computer simulator is proposed.…”

“…In O'uchi et al (2002), fractal inter-connection networks are proposed, and the fractal inter-connection networks are used to avoid a network communication bottleneck. In NAKANISHI et al (2016), the register reordering method is proposed. It is shown that, by reordering registers, the number of memory access can be reduced.…”