A floating-gate-MOS-based low-power CDMA matched filter employing capacitance disconnection technique

Yamasaki, Tokiwa; Fukuda, T.; Shibata, Tadashi

doi:10.1109/vlsic.2003.1221223

Cited by 9 publications

(3 citation statements)

References 7 publications

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“…A second reason for working with MIFGMOS is that it permits the creation of new design strategies due to the large number of degrees of freedom that are generated by having many control gates. Thus, it is possible to create new architectures, for example, [17] and [18]. In addition, according to (1), V FG is an approximation of the weighted sum of the voltages applied to the control gates (it is an approximation because the parasitic effects have influence in the real calculus), which leads to the generation of interesting signal processors, for example, [19,20].…”

Section: Device Propertiesmentioning

confidence: 99%

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Analysis of the floating‐gate transistor using the charge sheet model

Medina-Vazquez

Meda-Campana

Gurrola-Navarro

et al. 2015

Int J Numerical Modelling

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The multiple-input floating-gate transistor is a semiconductor device that has found wide application in digital and analog electronic integrated circuits. Simulating an electronic circuit is an essential step in the design flow, prior to manufacturing. Therefore, an advanced model for the multiple-input floating-gate transistor is needed for analog design. This paper shows a method for adapting the charge sheet model for advanced models of the device. In addition, the problem of obtaining the drain to source current numerically as a function of external voltages is addressed. Furthermore, important plots are presented in order to clarify the behavior of the concerned device. The small signal analysis of the device is included. This summary may be interesting to those seeking to model the multiple-input floating-gate transistor, looking for alternatives to analog electronic design, needing low operating voltage, generating new design strategies, or wishing to understand of the operation of the device or the use of alternatives to implement analog circuits. Figure 2. (a) Intrinsic interface for n-input gates MIFGMOS and (b) MOS interface with a new terminal added (c) capacitances are represented only. 678 A. S. MEDINA-VAZQUEZ ET AL.Figure 3. ψ s vs. (V 1 À V FB ).Simulation results for the intrinsic interface. Voltage V 1 is applied to the control gate CG 1 and swept while V 2 voltage (applied to the control gate CG 2 ) is used as a parameter. V FB = 0.6 V, t ox = 8e À 9 m, W = 0.3 μm, W = 0.1 μm, C 1 = 50 fF, C 2 = 20 fF.

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Section: Device Propertiesmentioning

confidence: 99%

“…List of parameters used in Equations(1)(2)(3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16)(17)(18).…”

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Analysis of the floating‐gate transistor using the charge sheet model

Medina-Vazquez

Meda-Campana

Gurrola-Navarro

et al. 2015

Int J Numerical Modelling

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“…Considering only the detection after training, our filter improves the BER performance by a factor between 25 and 114, depending on the user. Other hardware implementations of CDMA detection [9] use less power and area than our filter, but they rely fundamentally on nonadaptive, strictly binary user signatures. Thus, these implementations can only operate in open loop using a traditional detection scheme.…”

Section: Application: Adaptive Cdma Despreadingmentioning

confidence: 99%

Adaptive signal processing in mixed-signal VLSI with anti-Hebbian learning

Figueroa

Matamala

Carvajal

et al. 2006

IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06)

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We describe analog and mixed-signal primitives for implementing adaptive signal-processing algorithms in VLSI based on anti-Hebbian learning. Both on-chip calibration techniques and the adaptive nature of the algorithms allow us to compensate for the effects of device mismatch. We use our primitives to implement a linear filter trained with the Least-Mean Squares (LMS) algorithm and an adaptive decorrelation network that improves the convergence of LMS. When applied to an adaptive Code-Division MultipleAccess (CDMA) despreading application, our system, without the need for power control, achieves more than 100x improvement in the bit-error ratio in the presence of high interference between users. Our 64-tap linear filter uses 0.25mm 2 of die area and dissipates 200μW in a 0.35μm CMOS process.

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