A full-duplex transceiver front-end employing inverse class-D power amplifiers

Ho, Wei-Gi; Singh, Vineet; Cho, Kunhee; Srinivasan, R.; Gharpurey, Ranjit

doi:10.1109/dcas.2016.7791143

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A 28-GHz Cascode Inverse Class-D Power Amplifier Utilizing Pulse Injection in 22-nm FDSOI

et al. 2020

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Current Mode Class-D (CMCD) Power Amplifiers are of particular interest in outphasing transmitters or Doherty configuration. This is because the output capacitance can be absorbed in the RLC output matching network and 100% theoretical efficiency. In this paper, a 28 GHz current mode (inverse) Class-D power amplifier was simulated, implemented, and measured in 22nm FDSOI. In order to overcome the breakdown voltages of the devices, the amplifier employs a stacked topology, which enables higher output powers and efficiency. The stacked transistors are also pulse injected to further increase the efficiency. Measurement results shows a peak PAE of 46%, peak drain efficiency (DE) of 71% and a saturated output power of 19 dBm. The implemented CMCD PA reports the best performance in literature compared to other CMOS based CMCD PAs.INDEX TERMS Current mode class-D, FDSOI CMOS, high efficiency, power added efficiency (PAE), power amplifier (PA), stacking.

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