A Fully Integrated 0.2V 802.11ba Wake-Up Receiver with -91.5dBm Sensitivity

Im, Jaeho; Breiholz, Jacob; Li, Shuo; Calhoun, Benton H.; Wenzloff, David D.

doi:10.1109/rfic49505.2020.9218383

Cited by 15 publications

(4 citation statements)

References 6 publications

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“…6a. A monolithic WuRx implementation including the front-end and the baseband using an integrated circuit would be ideal for the reduction in power consumption [32], [33]. Nevertheless, the off-the-shelf approach we have used allows us to provide a testbed for the evaluation of WuR-CTC that is both low-cost and flexible.…”

Section: E Wurx Implementationmentioning

confidence: 99%

Wake-Up Radio: An Enabler of Wireless Convergence

2021

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Section: E Wurx Implementationmentioning

confidence: 99%

Wake-Up Radio: An Enabler of Wireless Convergence

2021

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“…A dual IF architecture can reduce the LO accuracy requirement and improve the sensitivity to -97 dBm [3]. Heterodyne architecture with an integrated phase-locked loop (PLL) or frequency-locked loop (FLL) attracts more interest due to its superior sensitivity performance compared to others [4]- [6]. In addition, PLL techniques have been developed [7]- [9] and can reduce the cost of LO generation.…”

Section: Introductionmentioning

confidence: 99%

A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL

Zhang,

Duvvuri,

Bhattacharya

et al. 2024

IEEE Open J. Solid-State Circuits Soc.

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This paper presents a binary frequency-shift keying (BFSK) heterodyne wake-up receiver (WuRx) with -102 dBm sensitivity at 2.4 GHz. An integrated low-power all-digital phase-locked loop (ADPLL) allows sharp filtering at the intermediate frequency (IF) to improve sensitivity and interference robustness. The WuRx achieves an average current consumption of 2.2 µA to 171 µA range at 16 s to 0.1 s latency with the packet-level-duty-cycling scheme. In addition, it supports up to 60 channels from 2.300 GHz to 2.536 GHz. A signal-to-interference ratio (SIR) of -27/-30/-46 dB is achieved at 3/5/25 MHz offset from the carrier.INDEX TERMS All-digital phase-locked loop (ADPLL), Internet of Things (IoT), low-power, receivers, wake-up radios, wake-up receiver

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“…However, the high noise from the mixer-first structure significantly degrades the sensitivity. There is also a part of the study applied RF energy detection to directly convert the input RF signal to DC, which greatly reduces the power consumption due to the local oscillator (LO) and mixer, but also at the cost of sensitivity [12]- [16].…”

Section: Introductionmentioning

confidence: 99%

An N-Path Sub-GHz Ultra-Low Power Receiver Exploiting an N-Path Notch Filter Topology in 90 nm CMOS

Lei

et al. 2023

IEEE Access

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This paper describes an N-path sub-GHz ultra-low power receiver exploiting an N-path notch filter topology in 90nm CMOS process. The receiver achieves the flexibility in the operating frequency due to an adjustable internal impedance matching network with an N-path notch filter. The receiver consists of two current-reused topologies, which greatly simplifies the structure and achieves ultra-low power consumption. Specifically, the receiver incorporates: 1) an amplifier with an N-path notch filter, which acts as the first stage of the receiver to provide an input impedance of 50 Ω without an inductor. This input matching network is frequency flexible and adjustable to suit different frequencies of the input signal. Meanwhile, the N-path notch filter can suppress out-of-band interference to cope with limited frequency bands. 2) N-path passive mixers are reused for simultaneous filtering and down-conversion. 3) Amplifiers are frequency-division multiplexed to amplify both RF and baseband signals simultaneously. Finally, the receiver is fabricated in 90 nm CMOS and operates at 0.6 V supply voltage with a power consumption of 780 µW. The receiver achieves a conversion gain of 41.2 ± 3.2 dB, a noise figure of 5.7 ± 0.3 dB and an OB-IIP3 of 14.6 ± 0.5 dBm. The chip area of the implemented receiver is 0.08 µm 2 .INDEX TERMS CMOS, N-path notch filter, passive mixer, receiver, ultra-low power

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A Fully Integrated 0.2V 802.11ba Wake-Up Receiver with -91.5dBm Sensitivity

Cited by 15 publications

References 6 publications

Wake-Up Radio: An Enabler of Wireless Convergence

Wake-Up Radio: An Enabler of Wireless Convergence

A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL

An N-Path Sub-GHz Ultra-Low Power Receiver Exploiting an N-Path Notch Filter Topology in 90 nm CMOS

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