A fully integrated 900-MHz CMOS wireless receiver with on-chip RF and IF filters and 79-dB image rejection

Guo, Chunbing; Lo, Chi-Wa; Choi, Yu-Wing; Hsu, I.; Kan, T.K.K.; Leung, D.; Chan, Ann M.; Luong, Howard C.

doi:10.1109/jssc.2002.800981

Cited by 34 publications

References 8 publications

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On a class of cross coupled fully differential filters

Maundy

Elwakil

Gift

2015

Circuit Theory & Apps

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In this paper, a class of cross-coupled differential filters is presented. The filters implemented are second order, using two transistors cross-coupled surrounded by passive RLC components. The input of each filter is differential and so is its output. Biasing of each filter is straightforward, and the stability of the filters is examined. Several of the filters were built experimentally using discrete components and simulated using SPICE in a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) complementary metal-oxide semiconductor (CMOS) process, confirming the validity of the filters.

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On a class of cross coupled fully differential filters

Maundy

Elwakil

Gift

2015

Circuit Theory & Apps

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A novel, low‐complexity, high‐speed envelope detector and its applications

Ngo

Lee

Park

2011

Circuit Theory & Apps

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SUMMARYA compact and effective transmission envelope detector (TED), which can detect whether the absolute amplitude of an input differential signal is larger than a threshold or not, is proposed. The TED has been demonstrated to be applicable for received signal strength indicator circuit in wireless communication receivers or power management systems, and mode-control circuit in bidirectional optical transceivers. Implemented in a 0.18 m CMOS technology, the TED has a response time of 210 ps at 5 Gbps, occupies an active area of 0.05 mm 2 , and consumes 1 mA from 1.8 V supply.

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Design and optimization of LNA topologies with image rejection filters

Golmakani

Mafinejad

Kouzani

2010

Int J RF and Microwave Comp Aid Eng

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An important problem in designing RFIC in CMOS technology is the parasitic elements of passive and active devices that complicate design calculations. This article presents three LNA topologies including cascode, folded cascade, and differential cascode and then introduces image rejection filters for low-side and high-side injection. Then, a new method for design and optimization of the circuits based on a Pareto-based multiobjective genetic algorithm is proposed. A set of optimum device values and dimensions that best match design specifications are obtained. The optimization method is layout aware, parasitic aware, and simulation based. Circuit simulations are carried out based on TSMC 0.18 lm CMOS technology by using Hspice.

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A fully integrated 900-MHz CMOS wireless receiver with on-chip RF and IF filters and 79-dB image rejection

Cited by 34 publications

References 8 publications

On a class of cross coupled fully differential filters

On a class of cross coupled fully differential filters

A novel, low‐complexity, high‐speed envelope detector and its applications

Design and optimization of LNA topologies with image rejection filters

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