A Generalized Conflict-Free Memory Addressing Scheme for Continuous-Flow Parallel-Processing FFT Processors With Rescheduling

Tsai, Pei–Yun; Lin, Chau-Jy

doi:10.1109/tvlsi.2010.2077314

Cited by 54 publications

(29 citation statements)

References 18 publications

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“…The data at the output of the multiplexer is stored again in memory. The writing address is W 1 = c 1 c 0 , which is equal to R 0 to avoid memory access conflicts, as shown in (8). The memories are read according to R 1 = c 1 ⊕ m 1 , c 0 ⊕ m 0 .…”

Section: B Conflict-free Accessmentioning

confidence: 99%

See 1 more Smart Citation

A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices

Garrido

Sánchez

López‐Vallejo

et al. 2017

IEEE Trans. VLSI Syst.

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Abstract-This brief presents a novel 4096-point radix-4 memory-based FFT. The proposed architecture follows a conflictfree strategy that only requires a total memory of size N and few additional multiplexers. The control is also simple, as it is generated directly from the bits of a counter. Apart from the low complexity, the FFT has been implemented on a Virtex 5 FPGA using DSP slices. The goal has been to reduce the use of distributed logic, which is scarce in the target FPGA. With this purpose, most of the hardware has been implemented in DSP48E. As a result, the proposed FPGA is efficient in terms of hardware resources, as is shown by the experimental results.Index Terms-Fast Fourier Transform (FFT), Memory-based Architecture, Radix-4, Very-large-scale integration (VLSI), Field Programmable Gate Array (FPGA).

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Section: B Conflict-free Accessmentioning

confidence: 99%

“…They mainly differ in the size of the processing element (butterflies and rotators). The most typical approach is to use a radix-2 butterfly [3]- [5], but there are cases of radix-4 [6], [7] and other radices [8]- [11]. Memory-based FFTs also differ in the access strategy to the memory, which in most cases provides conflict-free access.…”

Section: Introductionmentioning

confidence: 99%

A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices

Garrido

Sánchez

López‐Vallejo

et al. 2017

IEEE Trans. VLSI Syst.

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show abstract

“…Memory-based architectures [12], [13] calculate the FFT iteratively on data stored in a memory. Pipelined architectures [3]- [9], [14], [15] calculate the FFT in a continuous flow.…”

Section: B the Fft Hardware Architecturesmentioning

confidence: 99%

Challenging the limits of FFT performance on FPGAs (Invited paper)

Garrido

Acevedo

Ehliar

et al. 2014

2014 International Symposium on Integrated Circuits (ISIC)

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Abstract-This paper analyzes the limits of FFT performance on FPGAs. For this purpose, a FFT generation tool has been developed. This tool is highly parameterizable and allows for generating FFTs with different FFT sizes and amount of parallelization. Experimental results for FFT sizes from 16 to 65536, and 4 to 64 parallel samples have been obtained. They show that even the largest FFT architectures fit well in today's FPGAs, achieving throughput rates from several GSamples/s to tens of GSamples/s.

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“…Continuous-flow mixed radix (CFMR) FFT. P. Y. Tsai and C. Y. Lin [9] utilizes two N-sample memories to generate a continuous output stream. One of the memories is used to calculate current FFT/IFFT symbols, while the other stores the previously computed results and controls the output sequence.…”

Section: Iiliterature Surveymentioning

confidence: 99%

Implementation of High Speed MDC FFT/IFFT Processor for MIMO-OFDM Systems

Basha¹,

L.Suneetha²

2014

IJAREEIE

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ABSTRACT:The architecture of multipath delay commutator (MDC) and memory scheduling are the basic concepts used to implement fast Fourier transform (FFT) processors with variable length. These FFT processors are used in orthogonal frequency division multiplexing systems, having multiple number of inputs and multiple number of outputs. Depending on this MDC architecture, we implement the fft/ifft processor based design which is proposed in this paper. In this design we implement ram, fifo, input buffer and output sorting buffer. The functionality verification and the synthesis is carried out using XILINX ISE 12.3i and shows the reduced delay values. KEYWORDS:Fast Fourier Transform (FFT), memory scheduling, multiple-input and multiple-output (MIMO), orthogonal frequency division multiplexing (OFDM), output sorting, pipeline based multipath delay commutator (MDC), WiMAX. I.INTRODUCTIONWhen we require a data to be encoded at multiple frequencies then the popular scheme generally used is orthogonal frequency division multiplexing. This type of scheme is famous at wideband digital communication. Whether it may be wired or wireless such as television, broadcasting of audio, internet accessing, wireless networks and is widely used in latest technology like 4G mobile communication. Digital multi carrier modulation technique is used for OFDM, When we require to carry parallel streaming of data, a large spaced orthogonal sub-carrier signals are used in which each sub-carrier undergo convolution modulation like quadrature amplitude modulation or phase shift keying. OFDM have capability of channel equalization because it uses slowly modulated narrow band signals instead of using one highly modulated wide band signal. Using OFDM, FFT can be implemented without loss in efficiency. Narrow band co channel interfacing becomes very robust using ofdm .it is very less sensitive over time synchronization errors. These type of OFDM signals have broad range of usage in WLAN under the standard of 802.11a,and digital radio systems standards like DAB/ERUKA 147,Terristial Digital TV systems(DVB-T)and Terrestrial Digital mobile systems(DVB-T) Fast Fourier transform are used to compute discrete Fourier transform and also for its inverse .These technique used to convert to signals from time to frequency domain and vice versa.fft makes numeric algorithm as simple such that it is used in image processing and signal processing applications. In previous DFT is existed ,in which the fastness drawback has overcome by fft.Ofdm uses reverse fft and transmitter side and fft and the receiver side to perform modulation and demodulation efficiently. Fft with ofdm is used cpu like intel Pentium at 1.26GHZ frequency and is able to calculate a 8 192 fft with in 576µs using FFTW, and in cpu called intel Pentium M AT 1.6 GHZ frequency and able to within 387 µs. a compared to earlier generation cpu ,a wide range of fft-ofdm based cpu named intel core 2 duo which operates at3 Ghz frequency and able to perform the operations at 96.MIMO-OFDM defines multi input a...

show abstract

A Generalized Conflict-Free Memory Addressing Scheme for Continuous-Flow Parallel-Processing FFT Processors With Rescheduling

Cited by 54 publications

References 18 publications

A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices

A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices

Challenging the limits of FFT performance on FPGAs (Invited paper)

Implementation of High Speed MDC FFT/IFFT Processor for MIMO-OFDM Systems

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