A generic broadband matching network synthesizer using real frequency technique

Wang, Fei; To, Chau

doi:10.1002/mmce.21227

Cited by 1 publication

(1 citation statement)

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“…Several iteration-based computer-aided broadband matching network design techniques are proposed in the literature in which real frequency technique (RFT), 26,27 Qfactor based impedance transformation (Q-fT), 28 and stepped impedance transmission line (SITL) 29,30 are widely used. The available state-of-the-art matching network design methods have their own merits and limitations.…”

Section: Related Workmentioning

confidence: 99%

A multi‐variable double impedance matching network design algorithm with design example of a low noise amplifier

Bajpai

Chauhan

2022

Int J RF Mic Comp-Aid Eng

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In this article, we propose a matching network design algorithm based on the segmentation of the real and imaginary part of optimum source impedance curve with respect to space variable x and frequency ω, respectively. The impedance curve (comprising of real and imaginary parts) is approximated as a collection of n linear segments, represented by the weighted sum of n semiinfinite linear functions. Using the numerical method, optimum weight vectors that maximize transducer power gain are obtained to model the real and imaginary parts of the source impedance curve. We get the values of optimum weight vectors and the rational input impedance function for the matching network, which are then synthesized in the desired topology by a continued partial fraction. Experimentally, we validate the novelty of the proposed method by designing matching networks of a wideband custom monolithic microwave integrated circuit (MMIC) low noise amplifier (LNA) in 1.3-2.3 GHz frequency band. The measured results of the designed LNA are significantly close to the simulated results. We bias our LNA at (5 V, 150 mA) and achieve a maximum noise figure of 1.25 dB, OP 1dB of 26 dBm, and an average TOI of 38 dBm. Moreover, our design of custom LNA MMIC has an integrated ESD structure while occupying only 0.32 mm 2 of chip area.

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