A generic programmable arbiter with default master grant

Pétrot, Frédéric; Hommais, Denis

doi:10.1109/iscas.2000.857610

Cited by 3 publications

(7 citation statements)

References 2 publications

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“…The priority at which requests are processed is driven via directly programmable control registers. This is a good and lightweight solution and a similar approach can be also found in [12], where authors introduce a very general register based architecture for TDMA communication infrastructure, as well as an algorithm for efficiently programming the hardware registers.…”

Section: Related Workmentioning

confidence: 98%

Adaptive TDMA bus allocation and elastic scheduling: A unified approach for enhancing robustness in multi-core RT systems

Burgio

Ruggiero

Esposito

et al. 2010

2010 IEEE International Conference on Computer Design

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Abstract-Next-generation real-time systems will be increasingly based on heterogeneous MPSoC design paradigms, where predictability and performance will be key issues to deal with. Such issues can be tackled both at the hardware level, by embedding technologies such as TDMA busses, and at the OS level, where suitable scheduling techniques can improve performance and reduce energy consumption. Among these, elastic scheduling has been proved to provide satisfactory results by dynamically reducing task periods at run-time to ensure the highest utilization possible of the processors. On the other hand, elastic scheduling lowers the degree of predictability and increases the complexity of the analysis at the system level. This reduces the benefits given by the TDMA bus, which relies on the high level task analysis for a robust and efficient slot allocation. Starting from this consideration, we propose a system where the elastic scheduling and the TDMA bus work synergistically. We introduce a QoS-aware adaptive bus service which takes the best of both techniques, mitigating their drawbacks at the same time. We show how the overhead introduced by coordination action is small, and it is however dominated by the benefits of the overall strategy in terms of performance and predictability guarantees.

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Section: Related Workmentioning

confidence: 98%

Adaptive TDMA bus allocation and elastic scheduling: A unified approach for enhancing robustness in multi-core RT systems

Burgio

Ruggiero

Esposito

et al. 2010

2010 IEEE International Conference on Computer Design

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“…[4], [10], [13] and [18]). These works focused on n-to-1 arbitration, where a request vector ('1' means a request) of n-bits is given, and an n-bit grant vector is generated with only one granting signal among n bits.…”

Section: Introductionmentioning

confidence: 99%

“…Communication (moving data from input to output port) follows switch configuration. In case of bus network applications ( [10]), the grant signal decides which source owns the bus in the next cycle to transmit data. In all of the above approaches, arbitration among n elements precedes the data movement.…”

Section: Introductionmentioning

confidence: 99%

“…N-bit arbiter circuits in each of [10], [13] and [18], were built in a tree structure, using 2-input or 4-input primitives. Critical delay path, which influences latency directly, extends from leaves to the root ( [10]) and in some cases, from leaves to the root and then back to leaves ( [13], [18]). [4] proposes a two-level design to reduce latency, which may work well for high number of inputs (n>2), however for 2-input arbiters a single level of logic gates would be sufficient.…”

Section: Introductionmentioning

confidence: 99%

“…The arbiters, proposed in [4] and [13] are based on priority encoder circuits. Priority encoders are simpler and faster, compared to circuits in [10] and [18]; however, they require support of extra circuits to provide fairness among requesting inputs. The above n-to-one arbiter circuits are not as useful for our purpose of implementing the pipelined binary tree.…”

Section: Introductionmentioning

confidence: 99%

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Arbitrate-and-move primitives for high throughput on-chip interconnection networks

Balkan

Vishkin

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

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An n-leaf pipelined balanced binary tree is used for arbitration of order and movement of data from n input ports to one output port. A novel arbitrate-and-move primitive circuit for every node of the tree, which is based on a concept of reduced synchrony that benefits from attractive features of both asynchronous and synchronous designs, is presented. The design objective of the pipelined binary tree is to provide a key building block in a high-throughput mesh-of-trees interconnection network for Explicit Multi Threading (XMT) architecture, a recently introduced parallel computation framework. The proposed reduced synchrony circuit was compared with asynchronous and synchronous designs of arbitrate-and-move primitives. Simulations with 0.18µm technology show that compared to an asynchronous design, the proposed reduced synchrony implementation achieves a higher throughput, up to 2 GigaRequests per second on an 8-leaf binary tree. Our circuit also consumes less power than the synchronous design, and requires less silicon area than both the synchronous and asynchronous designs.

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Programmable weighted arbiters for constructing switch schedulers

Yang

Zheng

Bhagyavati

et al.

2004 Workshop on High Performance Switching and Routing, 2004. HPSR.

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Abstract-As the basic building block of a scheduler based on maximal weight matching algorithms, the design of a weighted arbiter is vital to the performance of the scheduler. All existing weighted arbiter designs are based on the binary comparator tree structure and consume O(bN ) gates, where b is the number of bits needed to represent the weight. These designs are not desirable for implementing scheduling algorithms that require a large number of weighted arbiters. In light of the idea of radix sort, we propose a new weighted arbiter (WA) design and a programmable weighted arbiter (PWA) design, both with O(N ) gates. Through simulations, we show that the proposed WA design achieves significant improvement on area cost than existing WA designs. The proposed PWA design provides roundrobin fairness for requests with the same weight. Both designs can be directly used to build schedulers based on maximal weight matching algorithms. They are also useful for other applications, such as the arbitration of a shared bus and control of real-time systems.

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A generic programmable arbiter with default master grant

Cited by 3 publications

References 2 publications

Adaptive TDMA bus allocation and elastic scheduling: A unified approach for enhancing robustness in multi-core RT systems

Adaptive TDMA bus allocation and elastic scheduling: A unified approach for enhancing robustness in multi-core RT systems

Arbitrate-and-move primitives for high throughput on-chip interconnection networks

Programmable weighted arbiters for constructing switch schedulers

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