A gigabyte-per-second parallel fiber optic network interface for multimedia applications

Raghavan, Barath; Kim, Y.-G.; Chuang, T.; Madhavan, B.; Levi, A. F. J.

doi:10.1109/65.750446

Cited by 11 publications

(7 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…These attributes make commercial ONICs unusable for experimenting with new network architectures and VSR optical data links. On the other hand, an ONIC has been previously demonstrated that used custom-made integrated circuits to implement a specific network protocol [16]. While this approach successfully demonstrated the new network protocol proposed by its authors, it is difficult to modify this design because of the high cost and extensive knowledge required for the design of custom integrated circuits.…”

Section: A Network Interface Card Overviewmentioning

confidence: 99%

See 1 more Smart Citation

RATS: Reactive Architectures

Christensen¹,

Kiamelev²,

Haney³

et al. 2004

View full text Add to dashboard Cite

Public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing this collection of information. 12b. DISTRIBUTION CODE ABSTRACT (Maximum 200 Words)This project had two goals: To build an emulation prototype board for a tiled architecture and to demonstrate the utility of a global inter-chip free-space photonic interconnection fabric for polymorphous computer architectures (PCA). The free-space optics part of the project focused on two critical issues to validate the use of ultra-high-capacity global freespace interconnection fabrics for polymorphous computing architectures. These issues fell into the categories of interface issues and internal switch issues. The VCSEL-based free-space optical system was shown to be tolerant of misalignments, although electrical packaging problems prevented a full-performance demonstration. The optical links for the free-space system were demonstrated at 2.5 Gbps each with an inter-chip distance of about 10 cm. The project successfully demonstrated an optical inter-board fiber-based interconnect and intra-board free-space interconnect. The project also developed a prototype board that was demonstrated with an emulator of a tiled architecture.

show abstract

Section: A Network Interface Card Overviewmentioning

confidence: 99%

“…The differential resistance at 4 ~ 8 mA is 50 ohms and slope efficiency is 0.45 mW/mA. The die size of the VCSEL array is of 1.2 mm x 0.45 mm with 250 um pitch between each channel [16]. The Gallium Arsenide (GaAs) PIN Photodiode array operates with a responsivity of 0.5 A/W at 850 nm.…”

Section: D1 Oe Device Attachmentmentioning

confidence: 99%

RATS: Reactive Architectures

Christensen¹,

Kiamelev²,

Haney³

et al. 2004

View full text Add to dashboard Cite

show abstract

“…Myrinet, PONI (Parallel Optical Network Interconnection) and VIVACE have demonstrated its feasibility and superiority successfully 4,5,6 . Cut-through, store-and-forward LAN switching and free space optical switching techniques were introduced to realize high-performance real time data exchange 4,7,8 .…”

Section: Introductionmentioning

confidence: 98%

Design and analysis of high-performance switched optical interconnection network using WDM technology

et al. 2005

View full text Add to dashboard Cite

A high-performance switched optical interconnection network is designed. The top layer of optical fiber ring network builds upon wavelength division multiplexing and hardware routing technologies. The bottom layer of star network has a throughput of 10 Gbit/s based on an 8-channel digital cross-point switch. Two types of optical network interface cards are developed to meet the requirements of interconnection bandwidth and support PCI bus full bandwidth of 1.056 Gbit/s and 4.224 Gbit/s, respectively. Field programmable gate array (FPGA) is adopted for frame head analysis, hardware routing and dynamic switch configuration. By adding a subnet to enlarge the network, the maximal delay increment is only 1.5 µ s.

show abstract

“…The scheme of globally optimising deadline constraints presents an advantage over networks that don't arbitrate medium access on this property. Some examples of this may be found in [1], [2], [3], [4], [5]. However, these networks may have upper layer protocol added to them to give them better characteristics for real-time traffic but this increases the complexity of the system.…”

Section: Introductionmentioning

confidence: 99%