A Gm3 cancellation bias for 60GHz Doherty Power Amplifier

Tan, Aaron; Ma, Kaixue; Kong, Zhi Hui; Yeo, Kiat Seng

doi:10.1109/isocc.2015.7401785

Cited by 1 publication

(1 citation statement)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The DPA is one of the most popular techniques to enhance the efficiency of a PA, particularly at the back-off region where a PA would be favored to operate in as it would allow the PA to be in the linear operation. Its simplicity and potential are reviving the research of DPA in the recent years for sub 6GHz [24][25][26][27] as well as into the 60GHz region [28][29][30]. The DPA employs two PAs in different classes, typically class A, B and AB, combining the output power of the two PAs to increase the power range of the DPA and thus extends the efficiency range of the PA block.…”

Section: Introductionmentioning

confidence: 99%

An approach for circuit design optimization based on complexity considerations

Tan¹

View full text Add to dashboard Cite

Optimizing circuit trade-offs is a highly challenging task for any design team. This challenge is further exacerbated with the additional design complexity of integrating multiple circuits. Today, with the increasing demand for newer wireless communication products, design teams face a shorter time-to-market (TTM) for every generation of their new products and each product requires major improvement in wireless capability. Hence, it is important for the design teams to design circuits with complexity in mind. A design approach divided into architecture complexity, component complexity and discretional complexity are proposed. A novel benchmarking figure-of-merit, complexity factor (CF), was formulated and proposed for the architecture complexity. A simulated application of a goal, gain optimization, demonstrated and revealed that a reduction of up to 400% in the normalized complexity factor (NCF) could enhance the gain performance by approximately up to 40% for ultra-high frequency (UHF) applications. As the number of variables to be permuted is very high for the power amplifier (PA) blocks from circuit down to the process level, it is treated as a black box in the analysis but the next topology complexity step addressed this. A topology comparison was proposed between a 2-stacked EDNFET and SGNFET and a 4-stacked resistorladder SGNFET PA. Both of them achieved a near 20dBm output power and approximately 60% efficiency on the test-chips measurements, which demonstrated that the 2-stacked EDNFET and SGNFET topology with a reduction in stack height is a potential candidate for a reduced difficulty and complexity Doherty power amplifier (DPA) design. In the discretional complexity step, we explored the linearization of the DPA and proposed a DPA with a gm3 cancellation bias scheme tapping on its intrinsic linearization property, without adding external circuity to XII increase the complexity of the overall circuit but at the same time, improve its linearity by 6-8dB compared to a DPA optimized for power and more than 9dB compared with a balance PA with a similar structure. XIII

show abstract

Section: Introductionmentioning

confidence: 99%

An approach for circuit design optimization based on complexity considerations

Tan¹

View full text Add to dashboard Cite

show abstract

A Gm3 cancellation bias for 60GHz Doherty Power Amplifier

Cited by 1 publication

References 9 publications

An approach for circuit design optimization based on complexity considerations

An approach for circuit design optimization based on complexity considerations

Contact Info

Product

Resources

About