A GPS/Galileo SoC with adaptive in-band blocker cancellation in 65nm CMOS

Wu, Chhi‐Chong; Tsai, Wen-Chieh; Tan, Chun-Geik; Chen, Chun‐Nan; Li, Kuan-I; Hsu, Jui-Lin; Lo, Chi-Lun; Chen, Hsin‐Hua; Su, Sheng-Yuan; Chen, Kun-Tso; Chen, Min; Shanaa, Osama; Chou, Shu-Hung; Chien, George

doi:10.1109/isscc.2011.5746398

Cited by 16 publications

(5 citation statements)

References 3 publications

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“…Applications relying on GNSS positioning have become a part of everyday life, leading to an increased variety of Location-Based Services (LBS). Nowadays, the LBS consumer market is dominated by single frequency (typically L1/E1 band), low cost and highly integrated GNSS receivers [3][4][5][6][7][8][9]. The use of such receivers comes with two main limitations: low precision and low reliability.…”

Section: Introductionmentioning

confidence: 99%

NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor

Borejko

Marcinek

Siwiec

et al. 2020

Sensors

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A dual-frequency all-in-one Global Navigation Satellite System (GNSS) receiver with a multi-core 32-bit RISC (reduced instruction set computing) application processor was integrated and manufactured as a System-on-Chip (SoC) in a 110 nm CMOS (complementary metal-oxide semiconductor) process. The GNSS RF (radio frequency) front-end with baseband navigation engine is able to receive, simultaneously, Galileo (European Global Satellite Navigation System) E1/E5ab, GPS (US Global Positioning System) L1/L1C/L5, BeiDou (Chinese Navigation Satellite System) B1/B2, GLONASS (GLObal NAvigation Satellite System of Russian Government) L1/L3/L5, QZSS (Quasi-Zenith Satellite System development by the Japanese government) L1/L5 and IRNSS (Indian Regional Navigation Satellite System) L5, as well as all SBAS (Satellite Based Augmentation System) signals. The ability of the GNSS to detect such a broad range of signals allows for high-accuracy positioning. The whole SoC (system-on-chip), which is connected to a small passive antenna, provides precise position, velocity and time or raw GNSS data for hybridization with the IMU (inertial measurement unit) without the need for an external application processor. Additionally, user application can be executed directly in the SoC. It works in the −40 to +105 °C temperature range with a 1.5 V supply. The assembled test-chip takes 100 pins in a QFN (quad-flat no-leads) package and needs only a quartz crystal for the on-chip reference clock driver and optional SAW (surface acoustic wave) filters. The radio performance for both wideband (52 MHz) channels centered at L1/E1 and L5/E5 is NF = 2.3 dB, G = 131 dB, with 121 dBc/Hz of phase noise @ 1 MHz offset from the carrier, consumes 35 mW and occupies a 4.5 mm2 silicon area. The SoC reported in the paper is the first ever dual-frequency single-chip GNSS receiver equipped with a multi-core application microcontroller integrated with embedded flash memory for the user application program.

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Section: Introductionmentioning

confidence: 99%

NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor

Borejko

Marcinek

Siwiec

et al. 2020

Sensors

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show abstract

“…Location-based services (LBS) utilizing GNSS positioning have become a part of everyday life. Nowadays, the LBS consumer market is dominated by single-frequency GPS (US global positioning system) C/A (coarse acquisition signal) only and low-cost, highly integrated GNSS receivers [3][4][5][6][7][8][9]. However, low precision and low reliability are their main limitations.…”

Section: Introductionmentioning

confidence: 99%

GNSS-ISE: Instruction Set Extension for GNSS Baseband Processing

Marcinek

Pleskacz

2020

Sensors

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This work presents the results of research toward designing an instruction set extension dedicated to Global Navigation Satellite System (GNSS) baseband processing. The paper describes the state-of-the-art techniques of GNSS receiver implementation. Their advantages and disadvantages are discussed. Against this background, a new versatile instruction set extension for GNSS baseband processing is presented. The authors introduce improved mechanisms for instruction set generation focused on multi-channel processing. The analytical approach used by the authors leads to the introduction of a GNSS-instruction set extension (ISE) for GNSS baseband processing. The developed GNSS-ISE is simulated extensively using PC software and field-programmable gate array (FPGA) emulation. Finally, the developed GNSS-ISE is incorporated into the first-in-the-world, according to the authors’ best knowledge, integrated, multi-frequency, and multi-constellation microcontroller with embedded flash memory. Additionally, this microcontroller may serve as an application processor, which is a unique feature. The presented results show the feasibility of implementing the GNSS-ISE into an embedded microprocessor system and its capability of performing baseband processing. The developed GNSS-ISE can be implemented in a wide range of applications including smart IoT (internet of things) devices or remote sensors, fostering the adaptation of multi-frequency and multi-constellation GNSS receivers to the low-cost consumer mass-market.

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“…Conventionally, two surface acoustic wave (SAW) filters, before and after an external LNA, are used in state-of-art GNSS receivers to remove the out-of-band interference [3]. Recently, in order to reduce the number of off-chip components and increase the system integration level, efforts solving the problem of blockers to the GNSS receiver in cellular phones without SAW filter have been made [4]- [7].…”

Section: Introductionmentioning

confidence: 99%

SAW-less GNSS front-end amplifier with 80.4-dB GSM blocker suppression using CMOS directional coupler notch filter

Zheng

Chen

et al. 2013

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

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This paper presents a SAW-less GNSS front-end amplifier with GSM blocker suppression using CMOS directional coupler notch filter. The front-end amplifier is aimed at the GNSS receiver integrated in cellular phones. Based on our proposed CMOS stacked spiral-coupled (SSC) directional coupler working at the frequency of 900MHz as notch filter, the front end amplifier achieves a NF of 1.7dB and a 80.4-dB suppression of the GSM blocker while provides signal gain of 38.6-dB for the GPS L1-band signal.I.

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A GPS/Galileo SoC with adaptive in-band blocker cancellation in 65nm CMOS

Cited by 16 publications

References 3 publications

NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor

NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor

GNSS-ISE: Instruction Set Extension for GNSS Baseband Processing

SAW-less GNSS front-end amplifier with 80.4-dB GSM blocker suppression using CMOS directional coupler notch filter

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