A Greedy Heuristic for Process Mapping on Networks-on-Chip

Abstract

The state-of-the-art related to many-core processors focuses on Networks-on-Chip (NoCs) as approach to provide on-chip message-passing communication. The main problem is the number of hops from source to destination increasing the latency to exchange data based on network packets. Our goal is to propose a greedy heuristic for process mapping on NoCs clustering processes that have more communication on nearest cores. The evaluation method is based on simulation of parallel workloads on a NoC. The greedy heuristic achieves a higher throughput (up to 23.04%) and lower energy consumption (up to 9.87%) than a direct mapping approach for most workloads.