A hardware unit for fast SAH-optimised BVH construction

Abstract

Ray-tracing algorithms are known for producing highly realistic images, but at a significant computational cost. For this reason, a large body of research exists on various techniques for accelerating these costly algorithms. One approach to achieving superior performance which has received comparatively little attention is the design of specialised ray-tracing hardware. The research that does exist on this topic has consistently demonstrated that significant performance and efficiency gains can be achieved with dedicated microarchitectures. However, previous work on hardware ray-tracing has focused almost entirely on the traversal and intersection aspects of the pipeline. As a result, the critical aspect of the management and construction of acceleration data-structures remains largely absent from the hardware literature.We propose that a specialised microarchitecture for this purpose could achieve considerable performance and efficiency improvements over programmable platforms. To this end, we have developed the first dedicated microarchitecture for the construction of binned SAH BVHs. Cycle-accurate simulations show that our design achieves significant improvements in raw performance and in the bandwidth required for construction, as well as large efficiency gains in terms of performance per clock and die area compared to manycore implementations. We conclude that such a design would be useful in the context of a heterogeneous graphics processor, and may help future graphics processor designs to reduce predicted technology-imposed utilisation limits.

A hybrid fixed-function and microprocessor solution for high-throughput broad-phase collision detection

“…In particular, it would be interesting to experiment with shifting additional stages of the interactive application program loop from processors to microarchitectures. For instance, a microarchitecture for constructing BVHs [48] could complement ours. This would accept the k-d tree cells generated by the processor and construct or refit the BVHs associated with each cell.…”

“…To address this, we adapted the throughput metrics from the FPGA implementations to a clock frequency of 500 MHz in accordance with assumptions made in existing research [46][47][48]. Since 500 MHz is significantly lower than the clock frequencies of modern GPUs, we, therefore, derive a conservative estimate of throughput.…”

A Memory-Efficient Architecture of Full HD Around View Monitor Systems

“…There are some works related to the method of image rendering [21]- [23] and chip design for image rendering [24]. Because the methods in [21]- [23] are implemented on (GPU), in order to design an embedded system, a chip with GPU is indispensable.…”

“…Because the methods in [21]- [23] are implemented on (GPU), in order to design an embedded system, a chip with GPU is indispensable. Recently, most of the chips, including GPU as in [24], need DDR3 or DDR3L.…”

HART: A Hybrid Architecture for Ray Tracing Animated Scenes

“…Because most ray-tracing systems are based on acceleration data structures, such as kd-trees, bounding volume hierarchies (BVHs), and grids, these acceleration data structures should be effectively updated for dynamic scenes. Many researchers have exploited CPUs [1], [3], [4], [5], [6], [7], [8], [9], [10], [11], GPUs [12], [13], [14], [15], [16], MIC (many integrated core) [11], [17], or dedicated ray-tracing hardware [18], [19], [20] to achieve this goal.…”