A hierarchical image matting model for blood vessel segmentation in retinal images

Swathi, S.; Sushma, S.; Supraja, C. Devi; Bindusree, V.; Babitha, L.; Vijay, Vallabhuni

doi:10.1007/s13198-021-01397-0

Cited by 24 publications

(18 citation statements)

References 26 publications

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“…The inputs X(X31-X0), Y(Y31-Y0), 32-Bit Carry-Save Adder and the 16-Bit Adder are used [14]as the I/O components in the design of the block model of this improved 32-Bit Vedic Multiplier. Fig.…”

Section: Proposed Model Of the Improved Vedic Multipliermentioning

confidence: 99%

Realısatıon of Performance Optımısed 32-Bıt Vedıc Multıplıer

2023

VLSI

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This paper demonstrates the improved adaptation of the Vedic Multiplier using the Vedic standards, which includes old sutras. In this paper, current and proposed model are examined. Verilog HDL is utilized to execute the improved adaptation of Vedic Multiplier. Streamlined proposed model can likewise be utilized to achieve higher-request bits duplication exercises up to 32 bits. Vedic Multiplier up to 32-bit, the reproduction results are examined. These outcomes showed that the streamlined Vedic multiplier changed the execution improvement measurements, for example, time delay, also in device use too. Alongside this, a correlation is made among existing and enhanced proposed model to recognize about the presentation improvement measurements.

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Section: Proposed Model Of the Improved Vedic Multipliermentioning

confidence: 99%

Realısatıon of Performance Optımısed 32-Bıt Vedıc Multıplıer

2023

VLSI

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“…It happens because the source and drain terminals of the MOSFET become to be closer. [14][15][16][17][18][19][20][21] As a result of that, the gate terminal of the MOSFET starts to lose the control of the channel. Those undesirable effects which causes negative behaviour of transistor are called "short-channel effects" (SCE).…”

Section: Finfet Characteristics and Modellingmentioning

confidence: 99%

“…[3] Due to this property, it is popularly used for data error correction and detection in digital communication. [16][17][18][19][20][21] We know that the barrel shifter block plays a vital role in performance of the device from last chapter. Due to its importance, several studies were made by researchers to improve its performance for increasing its applications.…”

mentioning

confidence: 99%

Data Conversion: Realization of Code converter using Shift Register Modules

2023

VLSI

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Barrel shifter architecture is well known for bit manipulation in a single clock cycle. Due to its various operations and advantages, it is most likely used in the Arithmetic logic unit of every processor. Gray code is also known as reflective code which is widely used in digital communication for the purpose of error correction and error detection. In this project, an 8 x 4 barrel shifter is designed which is further connected to 4-bit binary to gray code converter. The barrel shifter is cascaded with binary to gray code converter so that this combination can be useful for the application of encryption of binary data in digital communications. It is designed in cadence virtuoso tool using FinFET technology at 18 nm node. The simulation results proves that the power consumed by the proposed design with FinFET technology is 11.92% less when compared with the conventional design with MOS transistors. Hence, this design can be used in application of low power digital communications. The functionality testing and verification is done using cadence virtuoso tool.

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“…The subsequent gate of FinFET can be utilized to control the limit voltage of the gadget, accordingly permitting quick turning on one side and diminished leakage current when circuits are inactive. [12][13][14][15][16][17] SRAM is one among the recollections for the most part utilized in the storage memory of gadgets. Memory Cells (SRAM) need to be quicker, consume less power devouring and reliable.…”

Section: Introductionmentioning

confidence: 99%

Flip-Flop Realization: Conventional Memory Elements Design with Transistor Nodes

2023

VLSI

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In the ultra-low-power implementation, center circuits of numerous frameworks are activated by inadequate occasions, for example, the Internet of Things (IoT) sensors and implantable clinical consideration. To guarantee that, the sensors get each and every occasion showing up whenever the circuits operate in standby mode the most of the time. Under such conditions, static power dominates in the total power consumption. For these implementations, the lessening framework leakage current can straightforwardly accomplish the greatest effectiveness of the complete framework power utilization. Since the SRAM cluster takes up a bigger bit of the circuit, it is important to decrease the power utilization of the SRAM exhibit so as to lessen circuit all-out power. Band-to-band tunneling (BTBT) mechanism introduced silicon tunnel FET (TFET), MOSFET compatible fabrication process and ultra-steep SS, which can break the 60mV/dec limitation of MOSFET at room temperature and ultralow off-state current. Subsequently, it is required to be a promising contender for an ultra-low-power rationale circuit. The impact of forward p-I-n leakage current could prompt harm to the static noise margin (SNM), static power and power defer result of the SRAM circuit. So the proposed topology can stay away from the p-I-n intersection, by expanding SRAM cell read and hold static noise margin (SNM) and diminishing static power utilization drastically.

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A hierarchical image matting model for blood vessel segmentation in retinal images

Cited by 24 publications

References 26 publications

Realısatıon of Performance Optımısed 32-Bıt Vedıc Multıplıer

Realısatıon of Performance Optımısed 32-Bıt Vedıc Multıplıer

Data Conversion: Realization of Code converter using Shift Register Modules

Flip-Flop Realization: Conventional Memory Elements Design with Transistor Nodes

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