A hierarchical test scheme for system-on-chip designs

Li, Jin-Fu; Huang, Hsin-Jung; Chen, Jeng-Bin; Su, Chih-Pin; Wu, Cheng‐Wen; Cheng, Chien‐Hong; Chen, Shao-I; Hwang, Chi-Yi; Lin, Hsin‐Piao

doi:10.1109/date.2002.998317

Cited by 5 publications

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

An Embedded Processor Based SOC Test Platform

Lee

Chu

Hong

2005 IEEE International Symposium on Circuits and Systems

View full text Add to dashboard Cite

In this paper we present a novel test platform for embedded processor based system-on-a-chip (SoC). The embedded processor is employed as a control kernel to execute the test programs for all the cores in the SoC. A dedicated Test Access Mechanism (TAM) controller is developed which controls the actual test procedure for each core such that no extra buffer is needed for individual cores. The TAM controller together with the test programs can execute scan-based testing, memory BIST and mixed-signal BIST. The platform can test cores wrapped by the standard boundary scan and the IEEE P1500 wrappers, as well as hierarchical and mixed-signal cores. Our methodology alleviates the need of expensive automatic test equipment (ATE), and hence can greatly reduce the total test cost. Experimental results show the effectiveness of the proposed test platform.I.

show abstract

An Embedded Processor Based SOC Test Platform

Lee

Chu

Hong

2005 IEEE International Symposium on Circuits and Systems

View full text Add to dashboard Cite

show abstract

Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling

Goel

Marinissen

Sehgal

et al. 2009

IEEE Trans. Comput.

View full text Add to dashboard Cite

Abstract-Many system-on-chip (SoC) integrated circuits today contain multiple hierarchy levels for both design and test. Hierarchy imposes constraints on the manner in which tests must be applied to "parent" cores and their "child" cores. However, most prior work on wrapper design, test access mechanism (TAM) optimization, and test scheduling is hierarchy oblivious, i.e., these techniques treat all cores in an SoC as if they are at the same level of hierarchy. We first show that the test architecture, consisting of wrappers and TAMs, and the corresponding test schedule designed for nonhierarchical SoCs are not valid for SoCs with hierarchical cores. Next, we present two approaches for efficient testing of SoCs with hierarchical cores. In the first approach, the problem is solved by extending a conventional wrapper design; this approach leaves full flexibility for TAM optimization and test scheduling. The second approach is based on a modified wrapper design for parent cores that operates in two disjoint modes for testing of parent and child cores. This approach has an impact on the test architecture and corresponding schedule. We show how an existing test architecture design algorithm can be adapted for use with both approaches. Experiments with the ITC'02 SoC Test Benchmarks show that the first approach offers lower test application times, while the second approach incurs less area costs.

show abstract

Multifrequency TAM design for hierarchical SOCs

Nicolici²

2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

Abstract-The emergence of megacores in hierarchical systemon-a-chip (SOC) presents new challenges to electronic test automation. This paper describes a new framework for designing test access mechanisms (TAMs) for modular testing of hierarchical SOCs. We first explore the concept that TAMs on the same level of design hierarchy employ multiple frequencies for test data transportation. Then we extend this concept to hierarchical SOCs and, by introducing frequency converters at the inputs and outputs of the megacores, the proposed solution not only removes the constraint that the system level TAM width must be wider than the internal TAM width of the megacores, but also facilitates rapid exploration of the tradeoffs between the test application time and the required test area. Experimental results for the ITC'02 SOC Test Benchmarks show that the proposed TAM design algorithms increase the size of the solution space that is explored, which, in turn, will lower the test application time when compared to the existing solutions.

show abstract

A hierarchical test scheme for system-on-chip designs

Cited by 5 publications

References 9 publications

An Embedded Processor Based SOC Test Platform

An Embedded Processor Based SOC Test Platform

Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling

Multifrequency TAM design for hierarchical SOCs

Contact Info

Product

Resources

About