A High-Performance and Flexible Architecture for Accelerating SDN on the MPSoC Platform

Abstract

Software-defined networking has been developing in recent years and the separation of the control plane and the data plane has made networks more flexible. Due to its flexibility, the software method is used to implement the data plane. However, with increasing network speed, the CPU is becoming unable to meet the requirements of high-speed packet processing. FPGAs are usually used as dumb switches to accelerate the data plane, with all intelligence centralized in the remote controller. However, the cost of taking the intelligence out of the switch is the increased latency between the controller and the switch. Therefore, we argue that the control decisions should be made as locally as possible. In this paper, we propose a novel architecture with high performance and flexibility for accelerating SDN based on the MPSoC platform. The control plane is implemented in the on-chip CPU and the data plane is implemented in the FPGA logic. The communication between the two components is performed using Ethernet communication. We design a high-performance TCAM based on distributed RAM. The architecture employs a pipeline design with modules connected via the AXI Stream interface. The designed architecture is flexible enough to support multiple network functions while achieving high performance at 100 Gbps. As far as we know, the architecture is the first proposed in the design of a 100 Gbps system.

High-Performance Reconfigurable Pipeline Implementation for FPGA-Based SmartNIC

“…The multiple match-action table (MMT) structure offers greater flexibility and effectively reduces the entry space requirement by employing multiple processing stages. In the case of the MMT structure, there are implementations like AccelSDP [13] or the design in [14] that utilize a multi-stage pipeline with several match-action tables. However, these implementations lack support for reconfiguring the match table and the pipeline itself.…”

“…This restricted configurability limits its flexibility. The pipeline described in [14] supports a greater number of stages, and the action performed within each stage can be configured with a controller. This provides more flexibility compared to AccelSDP.…”

“…Although the data plane of Drawerpipe has good flexibility and reconfigurability, its performance is very low and cannot meet the demand of a high-speed network. The work of AccelSDP [13] and M. Sha et al [14] both have high throughput, but their pipelines have limited flexibility. In the AccelSDP pipeline, the function of each stage is fixed, and the size and type of the match-action table is unchanged.…”

“…In the AccelSDP pipeline, the function of each stage is fixed, and the size and type of the match-action table is unchanged. The pipeline of M. Sha et al [14] has higher flexibility than AccelSDP, and the ALU could perform some preset actions according the configuration, but its flexibility is still limited and its match tables are solidified. Compared with these methods, the designs of our work and Menshen's have more flexibility and more powerful packet processing.…”

Editorial for the Beyond Moore’s Law: Hardware Specialization and Advanced System on Chip

“…Specifically, Sha et al (reference [ 1 ]) present a design structure that integrates a CPU-based control plane and an FPGA-based data plane. Their aim is to support multiple network functions while achieving a high performance at 100 Gbps.…”