2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig) 2013
DOI: 10.1109/reconfig.2013.6732262
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A high performance architecture for computing burrows-wheeler transform on FPGAs

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Cited by 8 publications
(10 citation statements)
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“…Parallel algorithms and the hardware design of BWT are also studied to improve the speed, including the parallel architecture [3,15] and the practical hardware acceleration, for example, FPGA (field-programmable gate array) [16] and GPU (graphic processing unit) [17]. The advancement is that parallel algorithms benefit the hardware BWT performance, and the researchers tend to simplify the hardware design so that they can obtain higher speeds [3,17], but the algorithms such as SA-IS are still complex for the sensors.…”
Section: Journal Of Sensorsmentioning
confidence: 99%
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“…Parallel algorithms and the hardware design of BWT are also studied to improve the speed, including the parallel architecture [3,15] and the practical hardware acceleration, for example, FPGA (field-programmable gate array) [16] and GPU (graphic processing unit) [17]. The advancement is that parallel algorithms benefit the hardware BWT performance, and the researchers tend to simplify the hardware design so that they can obtain higher speeds [3,17], but the algorithms such as SA-IS are still complex for the sensors.…”
Section: Journal Of Sensorsmentioning
confidence: 99%
“…As shown in the first figure of [16], the principle of BWT is sorting the data to fit the compression. Sorting is the primary computation in BWT, which determines the performance.…”
Section: Cz-bwt Encoding and Decodingmentioning
confidence: 99%
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