A High-Performance Source Engineered Charge Plasma-Based Schottky MOSFET on SOI

Bashir, Faisal; Loan, Sajad A.; Rafat, M.; Alamoud, A.R.M.; Abbasi, Shuja A.

doi:10.1109/ted.2015.2464112

Cited by 72 publications

(33 citation statements)

References 25 publications

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“…Furthermore, realizing source and drain regions by ion implantation or diffusion methods requires a complex thermal budget and expensive thermal annealing techniques. Thus, in this scenario, dopingless (DL) devices are the potential candidates for replacement of conventional doped devices, because DL devices are free from doping‐related problems and can be fabricated at low temperature …”

Section: Introductionmentioning

confidence: 99%

Device and circuit level performance assessment of n‐ and p‐type dopingless MOSFETs

Bashir

Murshid

Banday

2018

Int J Numerical Modelling

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In this paper, two structures of n-and p-type dopingless MOSFETs have been presented and compared with conventional n-and p-type doped MOSFETs. The different regions of dopingless devices (n-and p-type dopingless MOSFETs) have been realized by using metal work function engineering: a charge plasma concept. The simulation studies of the doped (n-and p-type doped MOSFETs) and dopingless (n-and p-type dopingless MOSFETs) devices have been performed using Atlas 2D simulator. It has been observed that the dopingless devices outperform the conventional doped devices by sizeable margin. The various performance measuring parameters in which dopingless devices shows improvement in comparison with conventional doped devices are ON current (I on ), cutoff frequency ( f T ), subthreshold swing (SS). A comparative analysis for DL-nMOSFET shows 19% improvement in I on , 24% in f T , 1.5% in SS, approximately seven times in DIBL, and 38% in I on /I off . Almost similar improvement has been seen in DL-pMOSFET when compared conventional doped pMOSFET (D-pMOSFET). Besides this, Complementary MetalOxide Semiconductor (CMOS) inverter has been designed using doped-and dopingless-based MOSFETs. A significant improvement of 34.2% in switching delay has been achieved in the dopingless CMOS-based inverter. Further, it has been observed that the process variation effect at device and circuit level are almost negligible in dopingless-based devices and circuit configuration in comparison with conventional doped counterpart.

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Section: Introductionmentioning

confidence: 99%

Device and circuit level performance assessment of n‐ and p‐type dopingless MOSFETs

Bashir

Murshid

Banday

2018

Int J Numerical Modelling

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“…25 Here, the most crucial model invoked to emulate the Schottky tunneling across the electrode semiconductor interface are UST and Schottky barrier tunneling. 26 Figure 2.…”

Section: Device Structure and Simulation Frameworkmentioning

confidence: 99%

Contact engineered charge plasma junctionless transistor for suppressing tunneling leakage

Kumar

Singh

Priyadarshani

et al. 2020

Int J Numerical Modelling

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This work reports contact engineered charge plasma junctionless transistor (CE-CP-JLT) to suppress the tunneling leakage current by deploying calibrated exhaustive 2-D TCAD simulations. This analysis considered the detrimental effect due to the nonohmic source and drain side contacts by including universal Schottky tunneling and band-to-band tunneling models. Our study suggests to reduce the source/drain metal contacts to control the carriers tunneling in OFF state. This contact engineering can effectively minimizes the leakage with retained drive current capabilities. This would in turn improve the device switching behavior and I ON /I OFF current ratio at least by four orders. The reduction in leakage current leads to decrease in static power consumption. This facilitates the CE-CP-JLT deployment in a portable device for longer duration with same power supply. Further, the device sensitivity analysis with respect to electrode contact length, gate oxide thickness, dielectric constant, channel length and silicon film thickness is also analyzed. Moreover, the comparative analysis of device analog behavior is also carried out here. K E Y W O R D S band-to-band tunneling, charge plasma junctionless transistor, contact engineering, universal Schottky tunneling

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“…3b, an alignment of the Fermi levels of the metal (E FM ) and the semiconductor (E FS ) will occur to establish a thermal equilibrium. When the work-function of a metal (Φ M ) is smaller than the work-function of a semiconductor (Φ Sc ), electrons will get injected from the metal to semiconductor to shift its Fermilevel and results in degenerating the semiconductor [8][9][10][11][12][17][18][19][20][21][22] and induction of n-type CP. The induced n type plasma induced is given by [9,17,18]…”

Section: Physics Of Cp Creation In the Proposed Cp-based Hybrid Hemt mentioning

confidence: 99%

“…The cutoff frequency (f T ) of the conventional and the proposed hybrid HEMT has been computed using the following equation [22,24].…”

Section: Rf Performancementioning

confidence: 99%

Hybrid AlGaN/GaN high‐electron mobility transistor: design and simulation

Verma

Loan

Alamoud

et al. 2017

IET Circuits, Devices & Systems

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In this study, the authors propose a novel structure of high-electron mobility transistor (HEMT) with significantly improved performance. The novelty of the proposed HEMT is the realisation of two parallel induced electron layers under the source and drain electrode, one in the form of two-dimensional (2D) electron gas (2DEG) and the other in the form of charge plasma electron gas (CPEG). The proposed device is a hetrostructure GaN/AlGaN device, therefore, a 2DEG gets created. However, two metal electrodes at the source and drain terminals are used in the proposed device, which induce CPEG in an undoped AlGaN film under the source and drain electrode. Therefore, the proposed HEMT device is hybrid and has a combination of CPEG and the 2DEG. A two-dimensional (2D) calibrated simulation study of the proposed device has revealed that its hybrid nature has improved its performance significantly in comparison to the conventional HEMT device having 2DEG only. It has been observed that the ON current has enhanced by 115%, transconductance (g m) by 168%, cutoff frequency (f T) by 71% and maximum oscillation frequency (f max) by 65% in comparison to the conventional HEMT.

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A High-Performance Source Engineered Charge Plasma-Based Schottky MOSFET on SOI

Cited by 72 publications

References 25 publications

Device and circuit level performance assessment of n‐ and p‐type dopingless MOSFETs

Device and circuit level performance assessment of n‐ and p‐type dopingless MOSFETs

Contact engineered charge plasma junctionless transistor for suppressing tunneling leakage

Hybrid AlGaN/GaN high‐electron mobility transistor: design and simulation

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