A high resolution CMOS winner-take-all circuit

Abstract

A CMOS winner-take-all (WTA) circuit, which chooses one and only one winner for all possible input vector sets, is presented and its operation is explained. The circuit contains an excitatory feedback loop to increase both speed and resolution and an inhibitory feedback loop to prevent multiple winner selection. The proposed circuit limits the amount of positive feedback applied, automatically. Experimental results are presented to demonstrate the correct operation and hnctionality of the prototype chip fabricated in a 3-pm, n-well, CMOS technology. The chip operates at speeds up to 5 MHz without any observable tendency to multiple winner selection or instability even when the initial voltage differences between input nodes are small. It consumes less than 7mW for a single 5V supply. The circuit can be easily extended to a large scale for applications requiring large number of competitive cells. Its simple structure makes it highly suitable €or neural network hardware implementation and for signal processing applications.